📄 input.prd
字号:
[MCell 3 | 78| -| | ]
2 [IOpin 2 | 11| IO p7_2_|*|*]
[RegIn 2 | 80| -| | ]
[MCell 4 | 79| IO p7_2_| | ]
[MCell 5 | 81| IO p7_1_| | ]
3 [IOpin 3 | 12| IO p7_3_|*|*]
[RegIn 3 | 83| -| | ]
[MCell 6 | 82| -| | ]
[MCell 7 | 84| -| | ]
4 [IOpin 4 | 13| IO p8_6_|*|*]
[RegIn 4 | 86| -| | ]
[MCell 8 | 85| IO p8_6_| | ]
[MCell 9 | 87| -| | ]
5 [IOpin 5 | 14| IO p8_7_|*|*]
[RegIn 5 | 89| -| | ]
[MCell 10 | 88| -| | ]
[MCell 11 | 90| -| | ]
6 [IOpin 6 | 15| -| | ]
[RegIn 6 | 92| -| | ]
[MCell 12 | 91| IO p7_3_| | ]
[MCell 13 | 93| -| | ]
7 [IOpin 7 | 16|INP cs|*|*]
[RegIn 7 | 95| -| | ]
[MCell 14 | 94| -| | ]
[MCell 15 | 96| -| | ]
---------------------------------------------------------------------------
===========================================================================
< Block [ 2] > Macrocell (MCell) Cluster Assignments
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size
| Sync/Async-------+ | | | Cluster to Mcell Assignment
| Node Fixed(*)----+ | | | | | +- XOR PT Size
| Sig Type-+ | | | | | | | XOR to Mcell Assignment
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
0| N_50_iZ0|NOD| | S | 2 | 4 to [ 0]| 1 XOR free
1| | ? | | S | | 4 free | 1 XOR free
2| | ? | | S | | 4 free | 1 XOR free
3| | ? | | S | | 4 free | 1 XOR free
4| un1_un19_wr|NOD| | A | 2 | 2 to [ 4]| 1 XOR free
5| | ? | | S | | 4 free | 1 XOR free
6| | ? | | S | | 4 free | 1 XOR free
7| | ? | | S | | 4 free | 1 XOR free
8| | ? | | S | | 4 free | 1 XOR free
9| | ? | | S | | 4 free | 1 XOR free
10| | ? | | S | | 4 free | 1 XOR free
11| | ? | | S | | 4 free | 1 XOR free
12| | ? | | S | | 4 free | 1 XOR free
13| | ? | | S | | 4 free | 1 XOR free
14| | ? | | S | | 4 free | 1 XOR free
15| | ? | | S | | 4 free | 1 XOR free
---------------------------------------------------------------------------
===========================================================================
< Block [ 2] > Maximum PT Capacity
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+
| Sync/Async-------+ | |
| Node Fixed(*)----+ | | |
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
0| N_50_iZ0|NOD| | S | 2 |=> can support up to [ 15] logic PT(s)
1| | ? | | S | |=> can support up to [ 15] logic PT(s)
2| | ? | | S | |=> can support up to [ 15] logic PT(s)
3| | ? | | S | |=> can support up to [ 15] logic PT(s)
4| un1_un19_wr|NOD| | A | 2 |=> can support up to [ 18] logic PT(s)
5| | ? | | S | |=> can support up to [ 15] logic PT(s)
6| | ? | | S | |=> can support up to [ 20] logic PT(s)
7| | ? | | S | |=> can support up to [ 20] logic PT(s)
8| | ? | | S | |=> can support up to [ 20] logic PT(s)
9| | ? | | S | |=> can support up to [ 20] logic PT(s)
10| | ? | | S | |=> can support up to [ 20] logic PT(s)
11| | ? | | S | |=> can support up to [ 20] logic PT(s)
12| | ? | | S | |=> can support up to [ 20] logic PT(s)
13| | ? | | S | |=> can support up to [ 20] logic PT(s)
14| | ? | | S | |=> can support up to [ 15] logic PT(s)
15| | ? | | S | |=> can support up to [ 10] logic PT(s)
---------------------------------------------------------------------------
===========================================================================
< Block [ 2] > Node-Pin Assignments
===========================================================================
+ Macrocell Number
| Node Fixed(*)------+
| Sig Type---+ | to | Block [ 2] IO Pin | Device Pin
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
0| N_50_iZ0|NOD| | => | 5 6 7 0 | 22 21 20 27
1| | | | => | 5 6 7 0 | 22 21 20 27
2| | | | => | 6 7 0 1 | 21 20 27 26
3| | | | => | 6 7 0 1 | 21 20 27 26
4| un1_un19_wr|NOD| | => | 7 0 1 2 | 20 27 26 25
5| | | | => | 7 0 1 2 | 20 27 26 25
6| | | | => | 0 1 2 3 | 27 26 25 24
7| | | | => | 0 1 2 3 | 27 26 25 24
8| | | | => | 1 2 3 4 | 26 25 24 23
9| | | | => | 1 2 3 4 | 26 25 24 23
10| | | | => | 2 3 4 5 | 25 24 23 22
11| | | | => | 2 3 4 5 | 25 24 23 22
12| | | | => | 3 4 5 6 | 24 23 22 21
13| | | | => | 3 4 5 6 | 24 23 22 21
14| | | | => | 4 5 6 7 | 23 22 21 20
15| | | | => | 4 5 6 7 | 23 22 21 20
---------------------------------------------------------------------------
===========================================================================
< Block [ 2] > IO-to-Node Pin Mapping
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Node Destinations Via Output Matrix
_|_________________|__|___|_____|___________________________________________
0| adresse_5_|INP|*| 27| => | 0 1 2 3 4 5 6 7
1| adresse_4_|INP|*| 26| => | 2 3 4 5 6 7 8 9
2| adresse_3_|INP|*| 25| => | 4 5 6 7 8 9 10 11
3| adresse_2_|INP|*| 24| => | 6 7 8 9 10 11 12 13
4| adresse_1_|INP|*| 23| => | 8 9 10 11 12 13 14 15
5| adresse_0_|INP|*| 22| => | 10 11 12 13 14 15 0 1
6| wr|INP|*| 21| => | 12 13 14 15 0 1 2 3
7| rd|INP|*| 20| => | 14 15 0 1 2 3 4 5
---------------------------------------------------------------------------
===========================================================================
< Block [ 2] > IO/Node and IO/Input Macrocell Pairing Table
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Input Macrocell and Node Pairs
_|_________________|__|___|_____|__________________________________________
0| adresse_5_|INP|*| 27| => | Input macrocell [ -]
1| adresse_4_|INP|*| 26| => | Input macrocell [ -]
2| adresse_3_|INP|*| 25| => | Input macrocell [ -]
3| adresse_2_|INP|*| 24| => | Input macrocell [ -]
4| adresse_1_|INP|*| 23| => | Input macrocell [ -]
5| adresse_0_|INP|*| 22| => | Input macrocell [ -]
6| wr|INP|*| 21| => | Input macrocell [ -]
7| rd|INP|*| 20| => | Input macrocell [ -]
---------------------------------------------------------------------------
===========================================================================
< Block [ 2] > Input Multiplexer (IMX) Assignments
===========================================================================
+----- IO pin/Input Register, or Macrocell
IMX No. | +---- Block IO Pin or Macrocell Number
| | | ABEL Node/ +-- Signal using the Pin or Macrocell
| | | Pin Number | +- Signal Fixed (*) to Pin/Mcell
| | | | Sig Type | | +- Feedback Required (*)
---|-------|----|---|---|----------|------|-|------------------------------
0 [IOpin 0 | 27|INP adresse_5_|*|*]
[RegIn 0 | 98| -| | ]
[MCell 0 | 97|NOD N_50_iZ0| |*]
[MCell 1 | 99| -| | ]
1 [IOpin 1 | 26|INP adresse_4_|*|*]
[RegIn 1 |101| -| | ]
[MCell 2 |100| -| | ]
[MCell 3 |102| -| | ]
2 [IOpin 2 | 25|INP adresse_3_|*|*]
[RegIn 2 |104| -| | ]
[MCell 4 |103|NOD un1_un19_wr| |*]
[MCell 5 |105| -| | ]
3 [IOpin 3 | 24|INP adresse_2_|*|*]
[RegIn 3 |107| -| | ]
[MCell 6 |106| -| | ]
[MCell 7 |108| -| | ]
4 [IOpin 4 | 23|INP adresse_1_|*|*]
[RegIn 4 |110| -| | ]
[MCell 8 |109| -| | ]
[MCell 9 |111| -| | ]
5 [IOpin 5 | 22|INP adresse_0_|*|*]
[RegIn 5 |113| -| | ]
[MCell 10 |112| -| | ]
[MCell 11 |114| -| | ]
6 [IOpin 6 | 21|INP wr|*|*]
[RegIn 6 |116| -| | ]
[MCell 12 |115| -| | ]
[MCell 13 |117| -| | ]
7 [IOpin 7 | 20|INP rd|*|*]
[RegIn 7 |119| -| | ]
[MCell 14 |118| -| | ]
[MCell 15 |120| -| | ]
---------------------------------------------------------------------------
===========================================================================
< Block [ 2] > Logic Array Fan-in
===========================================================================
+- Central Switch Matrix No.
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
Mux00| ... | ...
Mux01| ... | ...
Mux02| IOPin 2 0 ( 27)| adresse_5_
Mux03| IOPin 2 2 ( 25)| adresse_3_
Mux04| IOPin 2 6 ( 21)| wr
Mux05| ... | ...
Mux06| Input Pin ( 29)| reset
Mux07| ... | ...
Mux08| IOPin 2 4 ( 23)| adresse_1_
Mux09| IOPin 2 1 ( 26)| adresse_4_
Mux10| IOPin 2 7 ( 20)| rd
Mux11| ... | ...
Mux12| Mcel 2 0 ( 97)| N_50_iZ0
Mux13| ... | ...
Mux14| ... | ...
Mux15| ... | ...
Mux16| IOPin 1 7 ( 16)| cs
Mux17| IOPin 2 5 ( 22)| adresse_0_
Mux18| ... | ...
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