📄 input.prd
字号:
13| | | | => | 3 4 5 6 | 48 47 46 45
14| | | | => | 4 5 6 7 | 47 46 45 44
15| | | | => | 4 5 6 7 | 47 46 45 44
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > IO-to-Node Pin Mapping
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Node Destinations Via Output Matrix
_|_________________|__|___|_____|___________________________________________
0| p2_7_| IO|*| 3| => | 0 1 2 3 4 ( 5) 6 7
1| p2_6_| IO|*| 2| => | 2 3 4 5 6 7 8 ( 9)
2| p2_5_| IO|*| 1| => | 4 5 ( 6) 7 8 9 10 11
3| p2_4_| IO|*| 48| => | 6 7 ( 8) 9 10 11 12 13
4| p2_3_| IO|*| 47| => | 8 9 10 11 (12) 13 14 15
5| p2_2_| IO|*| 46| => | 10 11 12 13 14 15 ( 0) 1
6| p2_1_| IO|*| 45| => | 12 13 14 15 0 ( 1) 2 3
7| p2_0_| IO|*| 44| => | 14 15 0 1 2 3 ( 4) 5
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > IO/Node and IO/Input Macrocell Pairing Table
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Input Macrocell and Node Pairs
_|_________________|__|___|_____|__________________________________________
0| p2_7_| IO|*| 3| => | Input macrocell [ -]
1| p2_6_| IO|*| 2| => | Input macrocell [ -]
2| p2_5_| IO|*| 1| => | Input macrocell [ -]
3| p2_4_| IO|*| 48| => | Input macrocell [ -]
4| p2_3_| IO|*| 47| => | Input macrocell [ -]
5| p2_2_| IO|*| 46| => | Input macrocell [ -]
6| p2_1_| IO|*| 45| => | Input macrocell [ -]
7| p2_0_| IO|*| 44| => | Input macrocell [ -]
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > Input Multiplexer (IMX) Assignments
===========================================================================
+----- IO pin/Input Register, or Macrocell
IMX No. | +---- Block IO Pin or Macrocell Number
| | | ABEL Node/ +-- Signal using the Pin or Macrocell
| | | Pin Number | +- Signal Fixed (*) to Pin/Mcell
| | | | Sig Type | | +- Feedback Required (*)
---|-------|----|---|---|----------|------|-|------------------------------
0 [IOpin 0 | 3| IO p2_7_|*|*]
[RegIn 0 | 50| -| | ]
[MCell 0 | 49| IO p2_2_| | ]
[MCell 1 | 51| IO p2_1_| | ]
1 [IOpin 1 | 2| IO p2_6_|*|*]
[RegIn 1 | 53| -| | ]
[MCell 2 | 52| -| | ]
[MCell 3 | 54| -| | ]
2 [IOpin 2 | 1| IO p2_5_|*|*]
[RegIn 2 | 56| -| | ]
[MCell 4 | 55| IO p2_0_| | ]
[MCell 5 | 57| IO p2_7_| | ]
3 [IOpin 3 | 48| IO p2_4_|*|*]
[RegIn 3 | 59| -| | ]
[MCell 6 | 58| IO p2_5_| | ]
[MCell 7 | 60| -| | ]
4 [IOpin 4 | 47| IO p2_3_|*|*]
[RegIn 4 | 62| -| | ]
[MCell 8 | 61| IO p2_4_| | ]
[MCell 9 | 63| IO p2_6_| | ]
5 [IOpin 5 | 46| IO p2_2_|*|*]
[RegIn 5 | 65| -| | ]
[MCell 10 | 64| -| | ]
[MCell 11 | 66| -| | ]
6 [IOpin 6 | 45| IO p2_1_|*|*]
[RegIn 6 | 68| -| | ]
[MCell 12 | 67| IO p2_3_| | ]
[MCell 13 | 69| -| | ]
7 [IOpin 7 | 44| IO p2_0_|*|*]
[RegIn 7 | 71| -| | ]
[MCell 14 | 70| -| | ]
[MCell 15 | 72| -| | ]
---------------------------------------------------------------------------
===========================================================================
< Block [ 1] > Macrocell (MCell) Cluster Assignments
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size
| Sync/Async-------+ | | | Cluster to Mcell Assignment
| Node Fixed(*)----+ | | | | | +- XOR PT Size
| Sig Type-+ | | | | | | | XOR to Mcell Assignment
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
0| p8_7_| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig
1| p7_0_| IO| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig
2| | ? | | S | | 4 free | 1 XOR free
3| | ? | | S | | 4 free | 1 XOR free
4| p7_2_| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig
5| p7_1_| IO| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig
6| | ? | | S | | 4 free | 1 XOR free
7| | ? | | S | | 4 free | 1 XOR free
8| p8_6_| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig
9| | ? | | S | | 4 free | 1 XOR free
10| | ? | | S | | 4 free | 1 XOR free
11| | ? | | S | | 4 free | 1 XOR free
12| p7_3_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig
13| | ? | | S | | 4 free | 1 XOR free
14| | ? | | S | | 4 free | 1 XOR free
15| | ? | | S | | 4 free | 1 XOR free
---------------------------------------------------------------------------
===========================================================================
< Block [ 1] > Maximum PT Capacity
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+
| Sync/Async-------+ | |
| Node Fixed(*)----+ | | |
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
0| p8_7_| IO| | S | 1 |=> can support up to [ 14] logic PT(s)
1| p7_0_| IO| | S | 1 |=> can support up to [ 19] logic PT(s)
2| | ? | | S | |=> can support up to [ 18] logic PT(s)
3| | ? | | S | |=> can support up to [ 18] logic PT(s)
4| p7_2_| IO| | S | 1 |=> can support up to [ 19] logic PT(s)
5| p7_1_| IO| | S | 1 |=> can support up to [ 19] logic PT(s)
6| | ? | | S | |=> can support up to [ 18] logic PT(s)
7| | ? | | S | |=> can support up to [ 19] logic PT(s)
8| p8_6_| IO| | S | 1 |=> can support up to [ 20] logic PT(s)
9| | ? | | S | |=> can support up to [ 19] logic PT(s)
10| | ? | | S | |=> can support up to [ 19] logic PT(s)
11| | ? | | S | |=> can support up to [ 19] logic PT(s)
12| p7_3_| IO| | S | 1 |=> can support up to [ 20] logic PT(s)
13| | ? | | S | |=> can support up to [ 19] logic PT(s)
14| | ? | | S | |=> can support up to [ 15] logic PT(s)
15| | ? | | S | |=> can support up to [ 10] logic PT(s)
---------------------------------------------------------------------------
===========================================================================
< Block [ 1] > Node-Pin Assignments
===========================================================================
+ Macrocell Number
| Node Fixed(*)------+
| Sig Type---+ | to | Block [ 1] IO Pin | Device Pin
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
0| p8_7_| IO| | => |( 5) 6 7 0 |( 14) 15 16 9
1| p7_0_| IO| | => | 5 6 7 ( 0)| 14 15 16 ( 9)
2| | | | => | 6 7 0 1 | 15 16 9 10
3| | | | => | 6 7 0 1 | 15 16 9 10
4| p7_2_| IO| | => | 7 0 1 ( 2)| 16 9 10 ( 11)
5| p7_1_| IO| | => | 7 0 ( 1) 2 | 16 9 ( 10) 11
6| | | | => | 0 1 2 3 | 9 10 11 12
7| | | | => | 0 1 2 3 | 9 10 11 12
8| p8_6_| IO| | => | 1 2 3 ( 4)| 10 11 12 ( 13)
9| | | | => | 1 2 3 4 | 10 11 12 13
10| | | | => | 2 3 4 5 | 11 12 13 14
11| | | | => | 2 3 4 5 | 11 12 13 14
12| p7_3_| IO| | => |( 3) 4 5 6 |( 12) 13 14 15
13| | | | => | 3 4 5 6 | 12 13 14 15
14| | | | => | 4 5 6 7 | 13 14 15 16
15| | | | => | 4 5 6 7 | 13 14 15 16
---------------------------------------------------------------------------
===========================================================================
< Block [ 1] > IO-to-Node Pin Mapping
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Node Destinations Via Output Matrix
_|_________________|__|___|_____|___________________________________________
0| p7_0_| IO|*| 9| => | 0 ( 1) 2 3 4 5 6 7
1| p7_1_| IO|*| 10| => | 2 3 4 ( 5) 6 7 8 9
2| p7_2_| IO|*| 11| => | ( 4) 5 6 7 8 9 10 11
3| p7_3_| IO|*| 12| => | 6 7 8 9 10 11 (12) 13
4| p8_6_| IO|*| 13| => | ( 8) 9 10 11 12 13 14 15
5| p8_7_| IO|*| 14| => | 10 11 12 13 14 15 ( 0) 1
6| | | | 15| => | 12 13 14 15 0 1 2 3
7| cs|INP|*| 16| => | 14 15 0 1 2 3 4 5
---------------------------------------------------------------------------
===========================================================================
< Block [ 1] > IO/Node and IO/Input Macrocell Pairing Table
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Input Macrocell and Node Pairs
_|_________________|__|___|_____|__________________________________________
0| p7_0_| IO|*| 9| => | Input macrocell [ -]
1| p7_1_| IO|*| 10| => | Input macrocell [ -]
2| p7_2_| IO|*| 11| => | Input macrocell [ -]
3| p7_3_| IO|*| 12| => | Input macrocell [ -]
4| p8_6_| IO|*| 13| => | Input macrocell [ -]
5| p8_7_| IO|*| 14| => | Input macrocell [ -]
6| | | | 15| => | Input macrocell [ -]
7| cs|INP|*| 16| => | Input macrocell [ -]
---------------------------------------------------------------------------
===========================================================================
< Block [ 1] > Input Multiplexer (IMX) Assignments
===========================================================================
+----- IO pin/Input Register, or Macrocell
IMX No. | +---- Block IO Pin or Macrocell Number
| | | ABEL Node/ +-- Signal using the Pin or Macrocell
| | | Pin Number | +- Signal Fixed (*) to Pin/Mcell
| | | | Sig Type | | +- Feedback Required (*)
---|-------|----|---|---|----------|------|-|------------------------------
0 [IOpin 0 | 9| IO p7_0_|*|*]
[RegIn 0 | 74| -| | ]
[MCell 0 | 73| IO p8_7_| | ]
[MCell 1 | 75| IO p7_0_| | ]
1 [IOpin 1 | 10| IO p7_1_|*|*]
[RegIn 1 | 77| -| | ]
[MCell 2 | 76| -| | ]
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