📄 input.prd
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|--------------------------------------------|
|- ispLEVER Fitter Report File -|
|- Version 2.01.28.41.02 -|
|- (c)Copyright, Lattice Semiconductor 2002 -|
|--------------------------------------------|
Start: Wed May 28 08:10:41 2003
End : Wed May 28 08:10:41 2003 $$$ Elapsed time: 00:00:00
===========================================================================
Part [C:\programme\ispTOOLS\ispcpld/dat/mach4a/mach468a] Design [input.tt4]
* Place/Route options (keycode = 540674)
= Spread Placement: ON
= No. Routing Attempts/Placement 2
* Placement Completion
+- Block +------- IO Pins Available
| +- Macrocells Available | +-- IO Pins Used
| | +- Signals to Place | | +----- Logic Array Inputs
| | | +- Placed | | | +- Array Inputs Used
_|____|____|____|_______________|____|_____________|___|________________
0 | 16 | 8 | 8 => 100% | 8 | 8 => 100% | 33 | 0 => 0%
1 | 16 | 6 | 6 => 100% | 8 | 7 => 87% | 33 | 0 => 0%
2 | 16 | 2 | 2 => 100% | 8 | 8 => 100% | 33 | 11 => 33%
3 | 16 | 8 | 8 => 100% | 8 | 8 => 100% | 33 | 25 => 75%
---|----|----|------------|-------|------------|-----|------------------
| Avg number of array inputs in used blocks : 18.00 => 54%
* Input/Clock Signal count: 10 -> placed: 10 = 100%
Resources Available Used
-----------------------------------------------------------------
Input Pins : 0 0 => 0%
I/O Pins : 32 31 => 96%
Clock Only Pins : 0 0 => 0%
Clock/Input Pins : 2 1 => 50%
Logic Blocks : 4 2 => 50%
Macrocells : 64 24 => 37%
PT Clusters : 64 8 => 12%
- Single PT Clusters : 64 16 => 25%
Input Registers : 0
* Routing Completion: 100%
* Attempts: Place [ 34] Route [ 0]
===========================================================================
Signal Fanout Table
===========================================================================
+- Signal Number
| +- Block Location ('+' for dedicated inputs)
| | +- Sig Type
| | | +- Signal-to-Pin Assignment
| | | | Fanout to Logic Blocks Signal Name
___|__|__|____|____________________________________________________________
1| 2|NOD| . |=> ..23| N_50_iZ0
2| 2|INP| 22|=> ..23| adresse_0_
3| 2|INP| 23|=> ..23| adresse_1_
4| 2|INP| 24|=> ..23| adresse_2_
5| 2|INP| 25|=> ..23| adresse_3_
6| 2|INP| 26|=> ..23| adresse_4_
7| 2|INP| 27|=> ..23| adresse_5_
8| 1|INP| 16|=> ..23| cs
9| 3|OUT| 33|=> ....| data_0_
10| 3|OUT| 34|=> ....| data_1_
11| 3|OUT| 35|=> ....| data_2_
12| 3|OUT| 36|=> ....| data_3_
13| 3|OUT| 37|=> ....| data_4_
14| 3|OUT| 38|=> ....| data_5_
15| 3|OUT| 39|=> ....| data_6_
16| 3|OUT| 40|=> ....| data_7_
17| 0| IO| 44|=> ...3| p2_0_
18| 0| IO| 45|=> ...3| p2_1_
19| 0| IO| 46|=> ...3| p2_2_
20| 0| IO| 47|=> ...3| p2_3_
21| 0| IO| 48|=> ...3| p2_4_
22| 0| IO| 1|=> ...3| p2_5_
23| 0| IO| 2|=> ...3| p2_6_
24| 0| IO| 3|=> ...3| p2_7_
25| 1| IO| 9|=> ...3| p7_0_
26| 1| IO| 10|=> ...3| p7_1_
27| 1| IO| 11|=> ...3| p7_2_
28| 1| IO| 12|=> ...3| p7_3_
29| 1| IO| 13|=> ...3| p8_6_
30| 1| IO| 14|=> ...3| p8_7_
31| 2|INP| 20|=> ..23| rd
32| +|INP| 29|=> ..2.| reset
33| 2|NOD| . |=> ...3| un1_un19_wr
34| 2|INP| 21|=> ..23| wr
---------------------------------------------------------------------------
===========================================================================
< C:\programme\ispTOOLS\ispcpld/dat/mach4a/mach468a Device Pin Assignments >
===========================================================================
+- Device Pin No
| Pin Type +- Signal Fixed (*)
| | | Signal Name
____|_____|_________|______________________________________________________
1 | I_O | 0_02|*| p2_5_
2 | I_O | 0_01|*| p2_6_
3 | I_O | 0_00|*| p2_7_
4 | JTAG | | | (pwr/test)
5 | CkIn | | | -
6 | JTAG | | | (pwr/test)
7 | GND | | | (pwr/test)
8 | JTAG | | | (pwr/test)
9 | I_O | 1_00|*| p7_0_
10 | I_O | 1_01|*| p7_1_
11 | I_O | 1_02|*| p7_2_
12 | I_O | 1_03|*| p7_3_
13 | I_O | 1_04|*| p8_6_
14 | I_O | 1_05|*| p8_7_
15 | I_O | 1_06| | -
16 | I_O | 1_07|*| cs
17 | Vcc | | | (pwr/test)
18 | JTAG | | | (pwr/test)
19 | GND | | | (pwr/test)
20 | I_O | 2_07|*| rd
21 | I_O | 2_06|*| wr
22 | I_O | 2_05|*| adresse_0_
23 | I_O | 2_04|*| adresse_1_
24 | I_O | 2_03|*| adresse_2_
25 | I_O | 2_02|*| adresse_3_
26 | I_O | 2_01|*| adresse_4_
27 | I_O | 2_00|*| adresse_5_
28 | JTAG | | | (pwr/test)
29 | CkIn | |*| reset
30 | JTAG | | | (pwr/test)
31 | GND | | | (pwr/test)
32 | JTAG | | | (pwr/test)
33 | I_O | 3_00|*| data_0_
34 | I_O | 3_01|*| data_1_
35 | I_O | 3_02|*| data_2_
36 | I_O | 3_03|*| data_3_
37 | I_O | 3_04|*| data_4_
38 | I_O | 3_05|*| data_5_
39 | I_O | 3_06|*| data_6_
40 | I_O | 3_07|*| data_7_
41 | Vcc | | | (pwr/test)
42 | JTAG | | | (pwr/test)
43 | GND | | | (pwr/test)
44 | I_O | 0_07|*| p2_0_
45 | I_O | 0_06|*| p2_1_
46 | I_O | 0_05|*| p2_2_
47 | I_O | 0_04|*| p2_3_
48 | I_O | 0_03|*| p2_4_
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > Macrocell (MCell) Cluster Assignments
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size
| Sync/Async-------+ | | | Cluster to Mcell Assignment
| Node Fixed(*)----+ | | | | | +- XOR PT Size
| Sig Type-+ | | | | | | | XOR to Mcell Assignment
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
0| p2_2_| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig
1| p2_1_| IO| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig
2| | ? | | S | | 4 free | 1 XOR free
3| | ? | | S | | 4 free | 1 XOR free
4| p2_0_| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig
5| p2_7_| IO| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig
6| p2_5_| IO| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig
7| | ? | | S | | 4 free | 1 XOR free
8| p2_4_| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig
9| p2_6_| IO| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig
10| | ? | | S | | 4 free | 1 XOR free
11| | ? | | S | | 4 free | 1 XOR free
12| p2_3_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig
13| | ? | | S | | 4 free | 1 XOR free
14| | ? | | S | | 4 free | 1 XOR free
15| | ? | | S | | 4 free | 1 XOR free
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > Maximum PT Capacity
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+
| Sync/Async-------+ | |
| Node Fixed(*)----+ | | |
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
0| p2_2_| IO| | S | 1 |=> can support up to [ 14] logic PT(s)
1| p2_1_| IO| | S | 1 |=> can support up to [ 19] logic PT(s)
2| | ? | | S | |=> can support up to [ 18] logic PT(s)
3| | ? | | S | |=> can support up to [ 18] logic PT(s)
4| p2_0_| IO| | S | 1 |=> can support up to [ 18] logic PT(s)
5| p2_7_| IO| | S | 1 |=> can support up to [ 18] logic PT(s)
6| p2_5_| IO| | S | 1 |=> can support up to [ 18] logic PT(s)
7| | ? | | S | |=> can support up to [ 17] logic PT(s)
8| p2_4_| IO| | S | 1 |=> can support up to [ 19] logic PT(s)
9| p2_6_| IO| | S | 1 |=> can support up to [ 19] logic PT(s)
10| | ? | | S | |=> can support up to [ 18] logic PT(s)
11| | ? | | S | |=> can support up to [ 19] logic PT(s)
12| p2_3_| IO| | S | 1 |=> can support up to [ 20] logic PT(s)
13| | ? | | S | |=> can support up to [ 19] logic PT(s)
14| | ? | | S | |=> can support up to [ 15] logic PT(s)
15| | ? | | S | |=> can support up to [ 10] logic PT(s)
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > Node-Pin Assignments
===========================================================================
+ Macrocell Number
| Node Fixed(*)------+
| Sig Type---+ | to | Block [ 0] IO Pin | Device Pin
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
0| p2_2_| IO| | => |( 5) 6 7 0 |( 46) 45 44 3
1| p2_1_| IO| | => | 5 ( 6) 7 0 | 46 ( 45) 44 3
2| | | | => | 6 7 0 1 | 45 44 3 2
3| | | | => | 6 7 0 1 | 45 44 3 2
4| p2_0_| IO| | => |( 7) 0 1 2 |( 44) 3 2 1
5| p2_7_| IO| | => | 7 ( 0) 1 2 | 44 ( 3) 2 1
6| p2_5_| IO| | => | 0 1 ( 2) 3 | 3 2 ( 1) 48
7| | | | => | 0 1 2 3 | 3 2 1 48
8| p2_4_| IO| | => | 1 2 ( 3) 4 | 2 1 ( 48) 47
9| p2_6_| IO| | => |( 1) 2 3 4 |( 2) 1 48 47
10| | | | => | 2 3 4 5 | 1 48 47 46
11| | | | => | 2 3 4 5 | 1 48 47 46
12| p2_3_| IO| | => | 3 ( 4) 5 6 | 48 ( 47) 46 45
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