input.out

TQ公司的STK16x开发系统的源码

34 "number of signals after reading design file"

"sig    sig    sig pair blk fan                       PT xor sync"
"num   name   type  sig num out             pin node cnt  PT type"
"---   ----   ---- ---- --- ---             --- ---- --- --- ----"

  47      p2_4_  5   -1   0   1           3  47   -1   1   0   21
  46      p2_3_  5   -1   0   1           3  46   -1   1   0   21
  45      p2_2_  5   -1   0   1           3  45   -1   1   0   21
  44      p2_1_  5   -1   0   1           3  44   -1   1   0   21
  43      p2_0_  5   -1   0   1           3  43   -1   1   0   21
  13      p8_7_  5   -1   1   1           3  13   -1   1   0   21
  12      p8_6_  5   -1   1   1           3  12   -1   1   0   21
  11      p7_3_  5   -1   1   1           3  11   -1   1   0   21
  10      p7_2_  5   -1   1   1           3  10   -1   1   0   21
   9      p7_1_  5   -1   1   1           3   9   -1   1   0   21
   8      p7_0_  5   -1   1   1           3   8   -1   1   0   21
   2      p2_7_  5   -1   0   1           3   2   -1   1   0   21
   1      p2_6_  5   -1   0   1           3   1   -1   1   0   21
   0      p2_5_  5   -1   0   1           3   0   -1   1   0   21
  39    data_7_  0        3   0              39   -1   2   0   20
  38    data_6_  0        3   0              38   -1   2   0   20
  35    data_3_  0        3   0              35   -1   2   0   20
  34    data_2_  0        3   0              34   -1   2   0   20
  33    data_1_  0        3   0              33   -1   2   0   20
  32    data_0_  0        3   0              32   -1   2   0   20
  37    data_5_  0        3   0              37   -1   1   0   20
  36    data_4_  0        3   0              36   -1   1   0   20
 146   N_50_iZ0  3   -1   2   2        2  3  -1   -1   2   0   21
 145 un1_un19_wr  3   -1   2   1           3  -1   -1   2   0   20
  26 adresse_5_  1   -1  -1   2        2  3  26   -1
  25 adresse_4_  1   -1  -1   2        2  3  25   -1
  24 adresse_3_  1   -1  -1   2        2  3  24   -1
  23 adresse_2_  1   -1  -1   2        2  3  23   -1
  22 adresse_1_  1   -1  -1   2        2  3  22   -1
  21 adresse_0_  1   -1  -1   2        2  3  21   -1
  20         wr  1   -1  -1   2        2  3  20   -1
  19         rd  1   -1  -1   2        2  3  19   -1
  15         cs  1   -1  -1   2        2  3  15   -1
  28      reset  1   -1  -1   1        2     28   -1