inputpld.vhd

TQ公司的STK16x开发系统的源码

library ieee;
use ieee.std_logic_1164.all;

entity Input_PLD is
	PORT	(
		 adresse:	IN	std_logic_vector (5 downto 0);
--		 clk	:	IN	std_logic;
		 reset	:	IN	std_logic;
		 rd     :	IN	std_logic;
		 wr 	:	IN	std_logic;
		 cs  	:	IN	std_logic;
		 data   :	INOUT 	std_logic_vector(7 downto 0);
		 p2     :	INOUT	std_logic_vector(7 downto 0);
		 p7	:	INOUT	std_logic_vector(3 downto 0); 
		 p8	:	INOUT	std_logic_vector(7 downto 6) 
		 );
--		 p9_5	:	INOUT	std_logic);
end Input_PLD; 

architecture Input of Input_PLD is
begin

sel_rd: process (cs, rd, wr, adresse, p2, p7, p8, reset) -- clk und reset in die sensitivity list! 	
begin

if reset ='0' then

	data <= "ZZZZZZZZ";
	p2 <= "ZZZZZZZZ";
        p7 <= "ZZZZ";
        p8 <= "ZZ";


elsif wr = '1' and rd = '0'then
  case cs&adresse is
    when "0001000" =>  data <= p2;
    when "0001001" =>  data(0) <= p7(0);
                       data(1) <= p7(1);
                       data(2) <= p7(2);
                       data(3) <= p7(3);
                       ---- data <= data and "00001111";
                       data(4) <= '0'; 
                       data(5) <= '0'; 
                       data(6) <= '0'; 
                       data(7) <= '0'; 
    when "0001010" =>  data(0) <= '0'; 
                       data(1) <= '0';              
                       data(2) <= '0'; 
                       data(3) <= '0'; 
                       data(4) <= '0'; 
                       data(5) <= '0'; 
                       data(6) <= p8(6);
                       data(7) <= p8(7);
                       ---- data <= data and "11000000";
    when others => data <= "ZZZZZZZZ";
    end case;
  elsif wr = '0' and rd = '1' then 
               	
--    case cs&adresse is
--      when "0001000" => p2 <= data;
--      when "0001001" => p7(0) <= data(0);
--                        p7(1) <= data(1);
--                        p7(2) <= data(2);
--                        p7(3) <= data(3);
--      when "0001010" => p8(6)  <= data(6);
--                        p8(7)  <= data(7);	
--      when others => 
		       data <= "ZZZZZZZZ";
--    end case;

  end if;
  end process;	

end Input;