input.vct

TQ公司的STK16x开发系统的源码

[DEVICE]
Family = M4A5;
PartType = M4A5-64/32;
Package = 48TQFP;
PartNumber = M4A5-64/32-55VC48;
Speed = -5.5;
Operating_condition = COM;
EN_Segment = No;
Pin_MC_1to1 = No;
EN_PinReserve_IO = Yes;
EN_PinReserve_BIDIR = Yes;
Voltage = 5.0;

[REVISION]
RCS = "$Revision: 1.5 $";
Parent = m4a5.lci;
SDS_File = m4a5.sds;
DATE = 05/27/2003;
TIME = 16:48:42;
Source_Format = Schematic_VHDL;
Type = TT2;
Pre_Fit_Time = 1;

[IGNORE ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;

[CLEAR ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;

[BACKANNOTATE ASSIGNMENTS]
Pin_Block = No;
Pin_Macrocell_Block = No;
Routing = No;

[GLOBAL PROJECT OPTIMIZATION]
Balanced_Partitioning = Yes;
Spread_Placement = Yes;
Max_Pin_Percent = 100;
Max_Macrocell_Percent = 100;

[OPTIMIZATION OPTIONS]
Logic_Reduction = Yes;
Max_PTerm_Split = 16;
Max_PTerm_Collapse = 16;
XOR_Synthesis = Yes;
EN_XOR_Synthesis = Yes;
XOR_Gate = Yes;
Node_Collapse = Yes;
Keep_XOR = Yes;
DT_Synthesis = Yes;
Clock_PTerm = Min;
Reset_PTerm = On;
Preset_PTerm = On;
Clock_Enable_PTerm = On;
Output_Enable_PTerm = On;
EN_DT_Synthesis = Yes;
Cluster_PTerm = 5;
FF_inv = No;
Speed = Yes;
EN_Use_CE = No;
Use_CE = No;
Use_Internal_COM_FB = Yes;
EN_use_Internal_COM_FB = Yes;
Set_Reset_Swap = No;
EN_Set_Reset_Swap = No;
Density = No;
DeMorgan = Yes;
T_FF = Yes;
Max_Symbols = 32;

[FITTER GLOBAL OPTIONS]
Run_Time = 0;
Set_Reset_Dont_Care = No;
EN_Set_Reset_Dont_Care = Yes;
In_Reg_Optimize = Yes;
EN_In_Reg_Optimize = No;
Clock_Optimize = No;
Global_Clock_As_Pterm = No;
Show_Iterations = No;
Routing_Attempts = 2;
Conf_Unused_IOs = Out_Low;

[HARDWARE DEVICE OPTIONS]
Zero_Hold_Time = No;
Signature_Word = 0;
Pull_up = No;
Out_Slew_Rate = FAST,SLOW,0;
Device_max_fanin = 33;
Device_max_pterms = 20;
Usercode_Format = Hex;

[PIN RESERVATIONS]
Layer = OFF;

[LOCATION ASSIGNMENT]
Layer = OFF;
adresse_0_ = input,22,-,-;
adresse_1_ = input,23,-,-;
adresse_2_ = input,24,-,-;
adresse_3_ = input,25,-,-;
adresse_4_ = input,26,-,-;
adresse_5_ = input,27,-,-;
cs = input,16,-,-;
rd = input,20,-,-;
wr = input,21,-,-;
p2_0_ = input,44,-,-;
p2_1_ = input,45,-,-;
p2_2_ = input,46,-,-;
p2_3_ = input,47,-,-;
p2_4_ = input,48,-,-;
p2_5_ = input,1,-,-;
p2_6_ = input,2,-,-;
p2_7_ = input,3,-,-;
p7_0_ = input,9,-,-;
p7_1_ = input,10,-,-;
p7_2_ = input,11,-,-;
p7_3_ = input,12,B,-;
data_0_ = input,33,-,-;
data_1_ = input,34,-,-;
data_2_ = input,35,-,-;
data_3_ = input,36,-,-;
data_4_ = input,37,-,-;
data_5_ = input,38,-,-;
data_6_ = input,39,-,-;
data_7_ = input,40,-,-;
p8_6_ = input,13,B,-;
p8_7_ = input,14,B,-;
reset = input,29,-,-;

[GROUP ASSIGNMENT]
Layer = OFF;

[SPACE RESERVATIONS]
Layer = OFF;

[BACKANNOTATE NETLIST]
Delay_File = SDF;
Netlist = VHDL;
VCC_GND = Cell;

[FITTER REPORT FORMAT]
Fitter_Options = Yes;
Pinout_Diagram = No;
Pinout_Listing = Yes;
Detailed_Block_Segment_Summary = Yes;
Input_Signal_List = Yes;
Output_Signal_List = Yes;
Bidir_Signal_List = Yes;
Node_Signal_List = Yes;
Signal_Fanout_List = Yes;
Block_Segment_Fanin_List = Yes;
Postfit_Eqn = Yes;
Page_Break = Yes;

[POWER]
Powerlevel =  Low,High;
Default = High;
Type = GLB;

[SOURCE CONSTRAINT OPTION]
Import_source_constraint = Yes;
Disable_warning_message = No;

[TIMING ANALYZER]
Last_source=;
Last_source_type=Fmax;

[INPUT REGISTERS]