input.nrp

TQ公司的STK16x开发系统的源码

ispLEVER 2.01.28.41.02 SDFGEN
Copyright(C),1992-2002, Lattice Semiconductor Corporation. All Rights Reserved.
Output Files:
  Netlist File: input.vho
  Delay   File: input.sdf

Parsing C:\programme\ispTOOLS\ispcpld/dat/sdf.mdl
Input file: w:\projekte\tqmx16xu\rev100a\sw\pld\input\input.tte
Reading library information ...
Mapping to combinational gates 
Mapping to netlist view.
Note 18862: NODE name N_50_iZ0 being renamed to GATE_data_7X_AR.
Utilization Estimate
    Combinational Macros:         48
    Flip-Flop and Latch Macros:    9
    I/O Pads:                     32
Elapsed time: 1 seconds