input_pld.tlg

TQ公司的STK16x开发系统的源码

Synthesizing work.input_pld.input
Post processing for work.input_pld.input
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal NoName, probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal data(0), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal NoName, probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal data(1), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal NoName, probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal data(2), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal NoName, probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal data(3), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal NoName, probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal data(4), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal NoName, probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal data(5), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal NoName, probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal data(6), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal NoName, probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd":26:0:26:1|Latch generated from process for signal data(7), probably caused by a missing assignment in an if or case stmt