input_pld.vm

TQ公司的STK16x开发系统的源码

//
// Written by Synplify
// Synplify Lite 7.1, Build 144R.
// Wed May 28 07:10:33 2003
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\c:\programme\isptools\synpbase\lib\vhd\std.vhd "
// file 2 "\w:\projekte\tqmx16xu\rev100a\sw\pld\input\inputpld.vhd "
// file 3 "\c:\programme\isptools\synpbase\lib\vhd\std1164.vhd "

`timescale 100 ps/100 ps
module IBUF (
  O,
  I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
  assign #(1)  O = I0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* IBUF */

module BUFTH (
  O,
  I0,
  OE
);
output O;
input I0;
input OE;
wire O ;
wire I0 ;
wire OE ;
wire [0:0] O_Z;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  O_Z[0] = OE ? I0 : 1'bz;
assign O = O_Z[0];
endmodule /* BUFTH */

module BI_DIR (
  O,
  I0,
  IO,
  OE
);
output O;
input I0;
inout IO;
input OE;
wire O ;
wire I0 ;
wire IO ;
wire OE ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  IO = OE ? I0 : 1'bz;
  assign #(1)  O = IO;
endmodule /* BI_DIR */

module INV (
  O,
  I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
  assign #(1)  O = ~ I0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* INV */

module AND2 (
  O,
  I0,
  I1
);
output O;
input I0;
input I1;
wire O ;
wire I0 ;
wire I1 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  O = I0  & I1 ;
endmodule /* AND2 */

module OR2 (
  O,
  I0,
  I1
);
output O;
input I0;
input I1;
wire O ;
wire I0 ;
wire I1 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  O = I0  | I1 ;
endmodule /* OR2 */

module MACH_LATCH (
  Q,
  D,
  LAT,
  R,
  S,
  NOTIFIER
);
output Q;
input D;
input LAT;
input R;
input S;
input NOTIFIER;
wire Q ;
wire D ;
wire LAT ;
wire R ;
wire S ;
wire NOTIFIER ;
wire un0 ;
wire un1 ;
wire true ;
wire false ;
  assign #(1)  un0 = ~ S;
  assign #(1)  un1 = ~ R;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1) Q = un1 ? 1'b0 : (un0 ? 1'b1 : (LAT ? D : Q )); // latrs
endmodule /* MACH_LATCH */

module DLATRH (
  Q,
  D,
  LAT,
  R
);
output Q;
input D;
input LAT;
input R;
wire Q ;
wire D ;
wire LAT ;
wire R ;
wire un0 ;
wire un1 ;
wire true ;
wire notifier ;
wire false ;
  MACH_LATCH INS5 (
	.Q(un0),
	.D(D),
	.LAT(LAT),
	.R(un1),
	.S(true),
	.NOTIFIER(notifier)
);
  assign #(1)  un1 = ~ R;
  assign true = 1'b1;
  assign false = 1'b0;
  assign notifier = 1'b0;
assign Q = un0;
endmodule /* DLATRH */

module Input_PLD (
  adresse,
  reset,
  rd,
  wr,
  cs,
  data,
  p2,
  p7,
  p8
);
input [5:0] adresse;
input reset;
input rd;
input wr;
input cs;
output [7:0] data;
inout [7:0] p2;
inout [3:0] p7;
inout [7:6] p8;
wire [5:0] adresse;
wire reset ;
wire rd ;
wire wr ;
wire cs ;
wire [7:0] data;
wire [7:0] p2;
wire [3:0] p7;
wire [7:6] p8;
wire [7:0] data_1;
wire [7:6] un1_p2;
wire [5:0] adresse_c;
wire [7:0] p2_c;
wire [3:0] p7_c;
wire [7:6] p8_c;
wire [5:0] adresse_c_i;
wire un1_un19_wr ;
wire GND ;
wire N_5 ;
wire N_7 ;
wire N_9 ;
wire N_11 ;
wire N_28 ;
wire N_29 ;
wire N_31 ;
wire N_32 ;
wire N_33 ;
wire N_34 ;
wire N_35 ;
wire N_36 ;
wire N_41 ;
wire \sel_rd.un19_wr  ;
wire N_45 ;
wire \sel_rd.un2_wr  ;
wire N_46 ;
wire reset_c ;
wire rd_c ;
wire wr_c ;
wire cs_c ;
wire N_50 ;
wire N_51 ;
wire N_57 ;
wire N_58 ;
wire N_59 ;
wire N_60 ;
wire N_61 ;
wire cs_c_i ;
wire wr_c_i ;
wire rd_c_i ;
wire N_45_i ;
wire N_51_i ;
wire N_50_i ;
wire \un1_p2_1_0_3_.un3  ;
wire \un1_p2_1_0_3_.un1  ;
wire \un1_p2_1_0_3_.un0  ;
wire \un1_p2_2_0_6_.un3  ;
wire \un1_p2_2_0_6_.un1  ;
wire \un1_p2_2_0_6_.un0  ;
wire \un1_p2_2_0_7_.un3  ;
wire \un1_p2_2_0_7_.un1  ;
wire \un1_p2_2_0_7_.un0  ;
wire \un1_p2_1_0_0_.un3  ;
wire \un1_p2_1_0_0_.un1  ;
wire \un1_p2_1_0_0_.un0  ;
wire \un1_p2_1_0_1_.un3  ;
wire \un1_p2_1_0_1_.un1  ;
wire \un1_p2_1_0_1_.un0  ;
wire \un1_p2_1_0_2_.un3  ;
wire \un1_p2_1_0_2_.un1  ;
wire \un1_p2_1_0_2_.un0  ;
wire VCC ;
//@1:1
  assign GND = 1'b0;
  IBUF \adresse_Z[0]  (
	.O(adresse_c[0]),
	.I0(adresse[0])
);
  IBUF \adresse_Z[1]  (
	.O(adresse_c[1]),
	.I0(adresse[1])
);
  IBUF \adresse_Z[2]  (
	.O(adresse_c[2]),
	.I0(adresse[2])
);
  IBUF \adresse_Z[3]  (
	.O(adresse_c[3]),
	.I0(adresse[3])
);
  IBUF \adresse_Z[4]  (
	.O(adresse_c[4]),
	.I0(adresse[4])
);
  IBUF \adresse_Z[5]  (
	.O(adresse_c[5]),
	.I0(adresse[5])
);
  IBUF reset_Z (
	.O(reset_c),
	.I0(reset)
);
  IBUF rd_Z (
	.O(rd_c),
	.I0(rd)
);
  IBUF wr_Z (
	.O(wr_c),
	.I0(wr)
);
  IBUF cs_Z (
	.O(cs_c),
	.I0(cs)
);
  BUFTH \data_Z[0]  (
	.O(data[0]),
	.I0(data_1[0]),
	.OE(un1_un19_wr)
);
  BUFTH \data_Z[1]  (
	.O(data[1]),
	.I0(data_1[1]),
	.OE(un1_un19_wr)
);
  BUFTH \data_Z[2]  (
	.O(data[2]),
	.I0(data_1[2]),
	.OE(un1_un19_wr)
);
  BUFTH \data_Z[3]  (
	.O(data[3]),
	.I0(data_1[3]),
	.OE(un1_un19_wr)
);
  BUFTH \data_Z[4]  (
	.O(data[4]),
	.I0(data_1[4]),
	.OE(un1_un19_wr)
);
  BUFTH \data_Z[5]  (
	.O(data[5]),
	.I0(data_1[5]),
	.OE(un1_un19_wr)
);
  BUFTH \data_Z[6]  (
	.O(data[6]),
	.I0(data_1[6]),
	.OE(un1_un19_wr)
);
  BUFTH \data_Z[7]  (
	.O(data[7]),
	.I0(data_1[7]),
	.OE(un1_un19_wr)
);
  BI_DIR \p2_Z[0]  (
	.O(p2_c[0]),
	.I0(GND),
	.IO(p2[0]),
	.OE(GND)
);
  BI_DIR \p2_Z[1]  (
	.O(p2_c[1]),
	.I0(GND),
	.IO(p2[1]),
	.OE(GND)
);
  BI_DIR \p2_Z[2]  (
	.O(p2_c[2]),
	.I0(GND),
	.IO(p2[2]),
	.OE(GND)
);
  BI_DIR \p2_Z[3]  (
	.O(p2_c[3]),
	.I0(GND),
	.IO(p2[3]),
	.OE(GND)
);
  BI_DIR \p2_Z[4]  (
	.O(p2_c[4]),
	.I0(GND),
	.IO(p2[4]),
	.OE(GND)
);
  BI_DIR \p2_Z[5]  (
	.O(p2_c[5]),
	.I0(GND),
	.IO(p2[5]),
	.OE(GND)
);
  BI_DIR \p2_Z[6]  (
	.O(p2_c[6]),
	.I0(GND),
	.IO(p2[6]),
	.OE(GND)
);
  BI_DIR \p2_Z[7]  (
	.O(p2_c[7]),
	.I0(GND),
	.IO(p2[7]),
	.OE(GND)
);
  BI_DIR \p7_Z[0]  (
	.O(p7_c[0]),
	.I0(GND),
	.IO(p7[0]),
	.OE(GND)
);
  BI_DIR \p7_Z[1]  (
	.O(p7_c[1]),
	.I0(GND),
	.IO(p7[1]),
	.OE(GND)
);
  BI_DIR \p7_Z[2]  (
	.O(p7_c[2]),
	.I0(GND),
	.IO(p7[2]),
	.OE(GND)
);
  BI_DIR \p7_Z[3]  (
	.O(p7_c[3]),
	.I0(GND),
	.IO(p7[3]),
	.OE(GND)
);
  BI_DIR \p8_Z[6]  (
	.O(p8_c[6]),
	.I0(GND),
	.IO(p8[6]),
	.OE(GND)
);
  BI_DIR \p8_Z[7]  (
	.O(p8_c[7]),
	.I0(GND),
	.IO(p8[7]),
	.OE(GND)
);
  INV \adresse_c_i_Z[0]  (
	.O(adresse_c_i[0]),
	.I0(adresse_c[0])
);
  INV \adresse_c_i_Z[1]  (
	.O(adresse_c_i[1]),
	.I0(adresse_c[1])
);
  INV N_51_i_Z (
	.O(N_51_i),
	.I0(N_51)
);
  INV N_50_i_Z (
	.O(N_50_i),
	.I0(N_50)
);
  AND2 G_19 (
	.O(N_46),
	.I0(N_57),
	.I1(N_59)
);
  AND2 \un1_p2_0_and2[5]  (
	.O(N_29),
	.I0(N_46),
	.I1(N_61)
);
  AND2 \un1_p2_0_and2[4]  (
	.O(N_28),
	.I0(N_46),
	.I1(N_60)
);
  AND2 G_19_38 (
	.O(N_57),
	.I0(adresse_c[3]),
	.I1(adresse_c_i[4])
);
  AND2 G_19_39 (
	.O(N_58),
	.I0(adresse_c_i[2]),
	.I1(cs_c_i)
);
  AND2 G_19_40 (
	.O(N_59),
	.I0(adresse_c_i[5]),
	.I1(N_58)
);
  AND2 un1_p2_0_and2_4_41 (
	.O(N_60),
	.I0(p2_c[4]),
	.I1(N_41)
);
  AND2 un1_p2_0_and2_5_42 (
	.O(N_61),
	.I0(p2_c[5]),
	.I1(N_41)
);
  INV \adresse_c_i_Z[5]  (
	.O(adresse_c_i[5]),
	.I0(adresse_c[5])
);
  INV \adresse_c_i_Z[2]  (
	.O(adresse_c_i[2]),
	.I0(adresse_c[2])
);
  INV cs_c_i_Z (
	.O(cs_c_i),
	.I0(cs_c)
);
  INV \adresse_c_i_Z[4]  (
	.O(adresse_c_i[4]),
	.I0(adresse_c[4])
);
  INV wr_c_i_Z (
	.O(wr_c_i),
	.I0(wr_c)
);
  INV rd_c_i_Z (
	.O(rd_c_i),
	.I0(rd_c)
);
  INV N_45_i_Z (
	.O(N_45_i),
	.I0(N_45)
);
  INV \un1_p2_1_0_3_.r  (
	.O(\un1_p2_1_0_3_.un3 ),
	.I0(adresse_c[0])
);
  AND2 \un1_p2_1_0_3_.m  (
	.O(\un1_p2_1_0_3_.un1 ),
	.I0(p7_c[3]),
	.I1(adresse_c[0])
);
  AND2 \un1_p2_1_0_3_.n  (
	.O(\un1_p2_1_0_3_.un0 ),
	.I0(p2_c[3]),
	.I1(\un1_p2_1_0_3_.un3 )
);
  OR2 \un1_p2_1_0_3_.p  (
	.O(N_11),
	.I0(\un1_p2_1_0_3_.un1 ),
	.I1(\un1_p2_1_0_3_.un0 )
);
  AND2 G_20 (
	.O(N_41),
	.I0(adresse_c_i[0]),
	.I1(adresse_c_i[1])
);
  AND2 G_21 (
	.O(N_51),
	.I0(adresse_c[0]),
	.I1(adresse_c[1])
);
  AND2 \sel_rd.un19_wr_0_and2  (
	.O(\sel_rd.un19_wr ),
	.I0(N_46),
	.I1(N_51_i)
);
  AND2 \un1_p2_2_0_0_and2[0]  (
	.O(N_31),
	.I0(N_5),
	.I1(adresse_c_i[1])
);
  AND2 \un1_p2_2_0_0_and2[1]  (
	.O(N_32),
	.I0(N_7),
	.I1(adresse_c_i[1])
);
  AND2 \un1_p2_2_0_0_and2[2]  (
	.O(N_33),
	.I0(N_9),
	.I1(adresse_c_i[1])
);
  AND2 \un1_p2_2_0_0_and2[3]  (
	.O(N_34),
	.I0(N_11),
	.I1(adresse_c_i[1])
);
  AND2 \un1_p2_1_0_0_and2[6]  (
	.O(N_35),
	.I0(adresse_c_i[0]),
	.I1(p2_c[6])
);
  AND2 \un1_p2_1_0_0_and2[7]  (
	.O(N_36),
	.I0(adresse_c_i[0]),
	.I1(p2_c[7])
);
  AND2 un1_un26_wr_0 (
	.O(N_50),
	.I0(N_45_i),
	.I1(reset_c)
);
  AND2 \sel_rd.un2_wr_0_and3  (
	.O(\sel_rd.un2_wr ),
	.I0(rd_c_i),
	.I1(wr_c)
);
  AND2 un1_un26_wr_0_and3 (
	.O(N_45),
	.I0(rd_c),
	.I1(wr_c_i)
);
  DLATRH un1_un19_wr_Z (
	.Q(un1_un19_wr),
	.D(\sel_rd.un19_wr ),
	.LAT(\sel_rd.un2_wr ),
	.R(N_50_i)
);
  DLATRH \data_1_Z[4]  (
	.Q(data_1[4]),
	.D(N_28),
	.LAT(\sel_rd.un2_wr ),
	.R(N_50_i)
);
  DLATRH \data_1_Z[5]  (
	.Q(data_1[5]),
	.D(N_29),
	.LAT(\sel_rd.un2_wr ),
	.R(N_50_i)
);
  DLATRH \data_1_Z[0]  (
	.Q(data_1[0]),
	.D(N_31),
	.LAT(\sel_rd.un2_wr ),
	.R(N_50_i)
);
  DLATRH \data_1_Z[1]  (
	.Q(data_1[1]),
	.D(N_32),
	.LAT(\sel_rd.un2_wr ),
	.R(N_50_i)
);
  DLATRH \data_1_Z[2]  (
	.Q(data_1[2]),
	.D(N_33),
	.LAT(\sel_rd.un2_wr ),
	.R(N_50_i)
);
  DLATRH \data_1_Z[3]  (
	.Q(data_1[3]),
	.D(N_34),
	.LAT(\sel_rd.un2_wr ),
	.R(N_50_i)
);
  DLATRH \data_1_Z[6]  (
	.Q(data_1[6]),
	.D(un1_p2[6]),
	.LAT(\sel_rd.un2_wr ),
	.R(N_50_i)
);
  DLATRH \data_1_Z[7]  (
	.Q(data_1[7]),
	.D(un1_p2[7]),
	.LAT(\sel_rd.un2_wr ),
	.R(N_50_i)
);
  INV \un1_p2_2_0_6_.r  (
	.O(\un1_p2_2_0_6_.un3 ),
	.I0(adresse_c[1])
);
  AND2 \un1_p2_2_0_6_.m  (
	.O(\un1_p2_2_0_6_.un1 ),
	.I0(p8_c[6]),
	.I1(adresse_c[1])
);
  AND2 \un1_p2_2_0_6_.n  (
	.O(\un1_p2_2_0_6_.un0 ),
	.I0(N_35),
	.I1(\un1_p2_2_0_6_.un3 )
);
  OR2 \un1_p2_2_0_6_.p  (
	.O(un1_p2[6]),
	.I0(\un1_p2_2_0_6_.un1 ),
	.I1(\un1_p2_2_0_6_.un0 )
);
  INV \un1_p2_2_0_7_.r  (
	.O(\un1_p2_2_0_7_.un3 ),
	.I0(adresse_c[1])
);
  AND2 \un1_p2_2_0_7_.m  (
	.O(\un1_p2_2_0_7_.un1 ),
	.I0(p8_c[7]),
	.I1(adresse_c[1])
);
  AND2 \un1_p2_2_0_7_.n  (
	.O(\un1_p2_2_0_7_.un0 ),
	.I0(N_36),
	.I1(\un1_p2_2_0_7_.un3 )
);
  OR2 \un1_p2_2_0_7_.p  (
	.O(un1_p2[7]),
	.I0(\un1_p2_2_0_7_.un1 ),
	.I1(\un1_p2_2_0_7_.un0 )
);
  INV \un1_p2_1_0_0_.r  (
	.O(\un1_p2_1_0_0_.un3 ),
	.I0(adresse_c[0])
);
  AND2 \un1_p2_1_0_0_.m  (
	.O(\un1_p2_1_0_0_.un1 ),
	.I0(p7_c[0]),
	.I1(adresse_c[0])
);
  AND2 \un1_p2_1_0_0_.n  (
	.O(\un1_p2_1_0_0_.un0 ),
	.I0(p2_c[0]),
	.I1(\un1_p2_1_0_0_.un3 )
);
  OR2 \un1_p2_1_0_0_.p  (
	.O(N_5),
	.I0(\un1_p2_1_0_0_.un1 ),
	.I1(\un1_p2_1_0_0_.un0 )
);
  INV \un1_p2_1_0_1_.r  (
	.O(\un1_p2_1_0_1_.un3 ),
	.I0(adresse_c[0])
);
  AND2 \un1_p2_1_0_1_.m  (
	.O(\un1_p2_1_0_1_.un1 ),
	.I0(p7_c[1]),
	.I1(adresse_c[0])
);
  AND2 \un1_p2_1_0_1_.n  (
	.O(\un1_p2_1_0_1_.un0 ),
	.I0(p2_c[1]),
	.I1(\un1_p2_1_0_1_.un3 )
);
  OR2 \un1_p2_1_0_1_.p  (
	.O(N_7),
	.I0(\un1_p2_1_0_1_.un1 ),
	.I1(\un1_p2_1_0_1_.un0 )
);
  INV \un1_p2_1_0_2_.r  (
	.O(\un1_p2_1_0_2_.un3 ),
	.I0(adresse_c[0])
);
  AND2 \un1_p2_1_0_2_.m  (
	.O(\un1_p2_1_0_2_.un1 ),
	.I0(p7_c[2]),
	.I1(adresse_c[0])
);
  AND2 \un1_p2_1_0_2_.n  (
	.O(\un1_p2_1_0_2_.un0 ),
	.I0(p2_c[2]),
	.I1(\un1_p2_1_0_2_.un3 )
);
  OR2 \un1_p2_1_0_2_.p  (
	.O(N_9),
	.I0(\un1_p2_1_0_2_.un1 ),
	.I1(\un1_p2_1_0_2_.un0 )
);
  assign VCC = 1'b1;
endmodule /* Input_PLD */