📄 input.vho
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-- VHDL netlist-file
library mach;
use mach.components.all;
library ieee;
use ieee.std_logic_1164.all;
entity Input_PLD is
port (
reset : in std_logic;
rd : in std_logic;
wr : in std_logic;
cs : in std_logic;
p2 : inout std_logic_vector(7 downto 0);
adresse : in std_logic_vector(5 downto 0);
p7 : inout std_logic_vector(3 downto 0);
p8 : inout std_logic_vector(7 downto 6);
data : out std_logic_vector(7 downto 0)
);
end Input_PLD;
architecture NetList of Input_PLD is
signal p2_2XPIN : std_logic;
signal p2_1XPIN : std_logic;
signal adresse_5XPIN : std_logic;
signal p2_0XPIN : std_logic;
signal p7_2XPIN : std_logic;
signal p7_1XPIN : std_logic;
signal p7_0XPIN : std_logic;
signal p2_7XPIN : std_logic;
signal p8_6XPIN : std_logic;
signal p7_3XPIN : std_logic;
signal p8_7XPIN : std_logic;
signal resetPIN : std_logic;
signal rdPIN : std_logic;
signal wrPIN : std_logic;
signal csPIN : std_logic;
signal adresse_4XPIN : std_logic;
signal adresse_3XPIN : std_logic;
signal adresse_2XPIN : std_logic;
signal adresse_1XPIN : std_logic;
signal adresse_0XPIN : std_logic;
signal p2_6XPIN : std_logic;
signal p2_5XPIN : std_logic;
signal p2_4XPIN : std_logic;
signal p2_3XPIN : std_logic;
signal data_7XQ : std_logic;
signal data_6XQ : std_logic;
signal data_5XQ : std_logic;
signal data_4XQ : std_logic;
signal data_3XQ : std_logic;
signal data_2XQ : std_logic;
signal data_1XQ : std_logic;
signal data_0XQ : std_logic;
signal un1_un19_wrQ : std_logic;
signal data_7X_D : std_logic;
signal data_7X_LH : std_logic;
signal data_6X_D : std_logic;
signal data_6X_LH : std_logic;
signal data_5X_D : std_logic;
signal data_5X_LH : std_logic;
signal data_4X_D : std_logic;
signal data_4X_LH : std_logic;
signal data_3X_D : std_logic;
signal data_3X_LH : std_logic;
signal data_2X_D : std_logic;
signal data_2X_LH : std_logic;
signal data_1X_D : std_logic;
signal data_1X_LH : std_logic;
signal data_0X_D : std_logic;
signal data_0X_LH : std_logic;
signal un1_un19_wr_D : std_logic;
signal un1_un19_wr_LH : std_logic;
signal data_7X_AR : std_logic;
signal T_0 : std_logic;
signal T_1 : std_logic;
signal T_2 : std_logic;
signal T_3 : std_logic;
signal T_4 : std_logic;
signal T_5 : std_logic;
signal T_6 : std_logic;
signal T_7 : std_logic;
signal T_8 : std_logic;
signal T_9 : std_logic;
signal T_10 : std_logic;
signal T_11 : std_logic;
signal T_12 : std_logic;
signal T_13 : std_logic;
signal T_14 : std_logic;
signal T_15 : std_logic;
signal T_16 : std_logic;
signal T_17 : std_logic;
signal T_18 : std_logic;
signal T_19 : std_logic;
signal T_20 : std_logic;
signal T_21 : std_logic;
signal T_22 : std_logic;
signal T_23 : std_logic;
signal T_24 : std_logic;
signal T_25 : std_logic;
signal T_26 : std_logic;
signal T_27 : std_logic;
signal T_28 : std_logic;
signal GND_net : std_logic;
signal GATE_data_7X_LH_A : std_logic;
signal GATE_data_6X_LH_A : std_logic;
signal GATE_data_5X_LH_A : std_logic;
signal GATE_data_4X_LH_A : std_logic;
signal GATE_data_3X_LH_A : std_logic;
signal GATE_data_2X_LH_A : std_logic;
signal GATE_data_1X_LH_A : std_logic;
signal GATE_data_0X_LH_A : std_logic;
signal GATE_un1_un19_wr_LH_A : std_logic;
signal GATE_data_7X_AR_A : std_logic;
signal GATE_T_2_A : std_logic;
signal GATE_T_3_A : std_logic;
signal GATE_T_3_B : std_logic;
signal GATE_T_4_A : std_logic;
signal GATE_T_5_A : std_logic;
signal GATE_T_5_B : std_logic;
signal GATE_T_6_A : std_logic;
signal GATE_T_7_A : std_logic;
signal GATE_T_7_B : std_logic;
signal GATE_T_8_A : std_logic;
signal GATE_T_9_A : std_logic;
signal GATE_T_9_B : std_logic;
signal GATE_T_10_A : std_logic;
signal GATE_T_10_B : std_logic;
signal GATE_T_12_A : std_logic;
signal GATE_T_13_A : std_logic;
signal GATE_T_13_B : std_logic;
signal GATE_T_16_A : std_logic;
signal GATE_T_19_A : std_logic;
signal GATE_T_21_A : std_logic;
signal GATE_T_23_A : std_logic;
signal GATE_T_25_A : std_logic;
signal GATE_T_27_A : std_logic;
begin
GND_I_I_1: GND port map ( X=>GND_net );
OUT_p2_2_I_1: BI_DIR port map ( O=>p2_2XPIN, I0=>GND_net, IO=>p2(2), OE=>GND_net );
OUT_p2_1_I_1: BI_DIR port map ( O=>p2_1XPIN, I0=>GND_net, IO=>p2(1), OE=>GND_net );
IN_adresse_5_I_1: IBUF port map ( O=>adresse_5XPIN, I0=>adresse(5) );
OUT_p2_0_I_1: BI_DIR port map ( O=>p2_0XPIN, I0=>GND_net, IO=>p2(0), OE=>GND_net );
OUT_p7_2_I_1: BI_DIR port map ( O=>p7_2XPIN, I0=>GND_net, IO=>p7(2), OE=>GND_net );
OUT_p7_1_I_1: BI_DIR port map ( O=>p7_1XPIN, I0=>GND_net, IO=>p7(1), OE=>GND_net );
OUT_p7_0_I_1: BI_DIR port map ( O=>p7_0XPIN, I0=>GND_net, IO=>p7(0), OE=>GND_net );
OUT_p2_7_I_1: BI_DIR port map ( O=>p2_7XPIN, I0=>GND_net, IO=>p2(7), OE=>GND_net );
OUT_p8_6_I_1: BI_DIR port map ( O=>p8_6XPIN, I0=>GND_net, IO=>p8(6), OE=>GND_net );
OUT_p7_3_I_1: BI_DIR port map ( O=>p7_3XPIN, I0=>GND_net, IO=>p7(3), OE=>GND_net );
OUT_p8_7_I_1: BI_DIR port map ( O=>p8_7XPIN, I0=>GND_net, IO=>p8(7), OE=>GND_net );
IN_reset_I_1: IBUF port map ( O=>resetPIN, I0=>reset );
IN_rd_I_1: IBUF port map ( O=>rdPIN, I0=>rd );
IN_wr_I_1: IBUF port map ( O=>wrPIN, I0=>wr );
IN_cs_I_1: IBUF port map ( O=>csPIN, I0=>cs );
IN_adresse_4_I_1: IBUF port map ( O=>adresse_4XPIN, I0=>adresse(4) );
IN_adresse_3_I_1: IBUF port map ( O=>adresse_3XPIN, I0=>adresse(3) );
IN_adresse_2_I_1: IBUF port map ( O=>adresse_2XPIN, I0=>adresse(2) );
IN_adresse_1_I_1: IBUF port map ( O=>adresse_1XPIN, I0=>adresse(1) );
IN_adresse_0_I_1: IBUF port map ( O=>adresse_0XPIN, I0=>adresse(0) );
OUT_p2_6_I_1: BI_DIR port map ( O=>p2_6XPIN, I0=>GND_net, IO=>p2(6), OE=>GND_net );
OUT_p2_5_I_1: BI_DIR port map ( O=>p2_5XPIN, I0=>GND_net, IO=>p2(5), OE=>GND_net );
OUT_p2_4_I_1: BI_DIR port map ( O=>p2_4XPIN, I0=>GND_net, IO=>p2(4), OE=>GND_net );
OUT_p2_3_I_1: BI_DIR port map ( O=>p2_3XPIN, I0=>GND_net, IO=>p2(3), OE=>GND_net );
OUT_data_7_I_1: BUFTH port map ( I0=>data_7XQ, O=>data(7), OE=>un1_un19_wrQ );
OUT_data_6_I_1: BUFTH port map ( I0=>data_6XQ, O=>data(6), OE=>un1_un19_wrQ );
OUT_data_5_I_1: BUFTH port map ( I0=>data_5XQ, O=>data(5), OE=>un1_un19_wrQ );
OUT_data_4_I_1: BUFTH port map ( I0=>data_4XQ, O=>data(4), OE=>un1_un19_wrQ );
OUT_data_3_I_1: BUFTH port map ( I0=>data_3XQ, O=>data(3), OE=>un1_un19_wrQ );
OUT_data_2_I_1: BUFTH port map ( I0=>data_2XQ, O=>data(2), OE=>un1_un19_wrQ );
OUT_data_1_I_1: BUFTH port map ( I0=>data_1XQ, O=>data(1), OE=>un1_un19_wrQ );
OUT_data_0_I_1: BUFTH port map ( I0=>data_0XQ, O=>data(0), OE=>un1_un19_wrQ );
LATCH_data_7_I_I: DLATRH port map ( Q=>data_7XQ, LAT=>data_7X_LH, R=>data_7X_AR, D=>data_7X_D );
LATCH_data_6_I_I: DLATRH port map ( Q=>data_6XQ, LAT=>data_6X_LH, R=>data_7X_AR, D=>data_6X_D );
LATCH_data_5_I_I: DLATRH port map ( Q=>data_5XQ, LAT=>data_5X_LH, R=>data_7X_AR, D=>data_5X_D );
LATCH_data_4_I_I: DLATRH port map ( Q=>data_4XQ, LAT=>data_4X_LH, R=>data_7X_AR, D=>data_4X_D );
LATCH_data_3_I_I: DLATRH port map ( Q=>data_3XQ, LAT=>data_3X_LH, R=>data_7X_AR, D=>data_3X_D );
LATCH_data_2_I_I: DLATRH port map ( Q=>data_2XQ, LAT=>data_2X_LH, R=>data_7X_AR, D=>data_2X_D );
LATCH_data_1_I_I: DLATRH port map ( Q=>data_1XQ, LAT=>data_1X_LH, R=>data_7X_AR, D=>data_1X_D );
LATCH_data_0_I_I: DLATRH port map ( Q=>data_0XQ, LAT=>data_0X_LH, R=>data_7X_AR, D=>data_0X_D );
LATCH_un1_un19_wr_I_I: DLATRH port map ( Q=>un1_un19_wrQ, LAT=>un1_un19_wr_LH, R=>data_7X_AR, D=>un1_un19_wr_D );
GATE_data_7X_D_I_1: OR2 port map ( O=>data_7X_D, I1=>T_14, I0=>T_13 );
GATE_data_7X_LH_I_1: AND2 port map ( O=>data_7X_LH, I1=>wrPIN, I0=>GATE_data_7X_LH_A );
GATE_data_7X_LH_I_2: INV port map ( O=>GATE_data_7X_LH_A, I0=>rdPIN );
GATE_data_6X_D_I_1: OR2 port map ( O=>data_6X_D, I1=>T_11, I0=>T_10 );
GATE_data_6X_LH_I_1: AND2 port map ( O=>data_6X_LH, I1=>wrPIN, I0=>GATE_data_6X_LH_A );
GATE_data_6X_LH_I_2: INV port map ( O=>GATE_data_6X_LH_A, I0=>rdPIN );
GATE_data_5X_D_I_1: AND4 port map ( O=>data_5X_D, I3=>T_25, I2=>T_26, I1=>T_27, I0=>T_28 );
GATE_data_5X_LH_I_1: AND2 port map ( O=>data_5X_LH, I1=>wrPIN, I0=>GATE_data_5X_LH_A );
GATE_data_5X_LH_I_2: INV port map ( O=>GATE_data_5X_LH_A, I0=>rdPIN );
GATE_data_4X_D_I_1: AND4 port map ( O=>data_4X_D, I3=>T_21, I2=>T_22, I1=>T_23, I0=>T_24 );
GATE_data_4X_LH_I_1: AND2 port map ( O=>data_4X_LH, I1=>wrPIN, I0=>GATE_data_4X_LH_A );
GATE_data_4X_LH_I_2: INV port map ( O=>GATE_data_4X_LH_A, I0=>rdPIN );
GATE_data_3X_D_I_1: OR2 port map ( O=>data_3X_D, I1=>T_9, I0=>T_8 );
GATE_data_3X_LH_I_1: AND2 port map ( O=>data_3X_LH, I1=>wrPIN, I0=>GATE_data_3X_LH_A );
GATE_data_3X_LH_I_2: INV port map ( O=>GATE_data_3X_LH_A, I0=>rdPIN );
GATE_data_2X_D_I_1: OR2 port map ( O=>data_2X_D, I1=>T_7, I0=>T_6 );
GATE_data_2X_LH_I_1: AND2 port map ( O=>data_2X_LH, I1=>wrPIN, I0=>GATE_data_2X_LH_A );
GATE_data_2X_LH_I_2: INV port map ( O=>GATE_data_2X_LH_A, I0=>rdPIN );
GATE_data_1X_D_I_1: OR2 port map ( O=>data_1X_D, I1=>T_5, I0=>T_4 );
GATE_data_1X_LH_I_1: AND2 port map ( O=>data_1X_LH, I1=>wrPIN, I0=>GATE_data_1X_LH_A );
GATE_data_1X_LH_I_2: INV port map ( O=>GATE_data_1X_LH_A, I0=>rdPIN );
GATE_data_0X_D_I_1: OR2 port map ( O=>data_0X_D, I1=>T_3, I0=>T_2 );
GATE_data_0X_LH_I_1: AND2 port map ( O=>data_0X_LH, I1=>wrPIN, I0=>GATE_data_0X_LH_A );
GATE_data_0X_LH_I_2: INV port map ( O=>GATE_data_0X_LH_A, I0=>rdPIN );
GATE_un1_un19_wr_D_I_1: OR2 port map ( O=>un1_un19_wr_D, I1=>T_1, I0=>T_0 );
GATE_un1_un19_wr_LH_I_1: AND2 port map ( O=>un1_un19_wr_LH, I1=>wrPIN, I0=>GATE_un1_un19_wr_LH_A );
GATE_un1_un19_wr_LH_I_2: INV port map ( O=>GATE_un1_un19_wr_LH_A, I0=>rdPIN );
GATE_data_7X_AR_I_1: NAN2 port map ( O=>data_7X_AR, I0=>resetPIN, I1=>GATE_data_7X_AR_A );
GATE_data_7X_AR_I_2: INV port map ( O=>GATE_data_7X_AR_A, I0=>T_12 );
GATE_T_0_I_1: AND3 port map ( O=>T_0, I2=>T_19, I1=>T_20, I0=>T_18 );
GATE_T_1_I_1: AND3 port map ( O=>T_1, I2=>T_16, I1=>T_17, I0=>T_15 );
GATE_T_2_I_1: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_2_A );
GATE_T_2_I_2: AND3 port map ( O=>T_2, I2=>adresse_0XPIN, I1=>p7_0XPIN, I0=>GATE_T_2_A );
GATE_T_3_I_1: INV port map ( I0=>adresse_0XPIN, O=>GATE_T_3_A );
GATE_T_3_I_2: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_3_B );
GATE_T_3_I_3: AND3 port map ( O=>T_3, I0=>p2_0XPIN, I2=>GATE_T_3_A, I1=>GATE_T_3_B );
GATE_T_4_I_1: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_4_A );
GATE_T_4_I_2: AND3 port map ( O=>T_4, I2=>adresse_0XPIN, I1=>p7_1XPIN, I0=>GATE_T_4_A );
GATE_T_5_I_1: INV port map ( I0=>adresse_0XPIN, O=>GATE_T_5_A );
GATE_T_5_I_2: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_5_B );
GATE_T_5_I_3: AND3 port map ( O=>T_5, I0=>p2_1XPIN, I2=>GATE_T_5_A, I1=>GATE_T_5_B );
GATE_T_6_I_1: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_6_A );
GATE_T_6_I_2: AND3 port map ( O=>T_6, I2=>adresse_0XPIN, I1=>p7_2XPIN, I0=>GATE_T_6_A );
GATE_T_7_I_1: INV port map ( I0=>adresse_0XPIN, O=>GATE_T_7_A );
GATE_T_7_I_2: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_7_B );
GATE_T_7_I_3: AND3 port map ( O=>T_7, I0=>p2_2XPIN, I2=>GATE_T_7_A, I1=>GATE_T_7_B );
GATE_T_8_I_1: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_8_A );
GATE_T_8_I_2: AND3 port map ( O=>T_8, I2=>adresse_0XPIN, I1=>p7_3XPIN, I0=>GATE_T_8_A );
GATE_T_9_I_1: INV port map ( I0=>adresse_0XPIN, O=>GATE_T_9_A );
GATE_T_9_I_2: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_9_B );
GATE_T_9_I_3: AND3 port map ( O=>T_9, I0=>p2_3XPIN, I2=>GATE_T_9_A, I1=>GATE_T_9_B );
GATE_T_10_I_1: INV port map ( I0=>adresse_0XPIN, O=>GATE_T_10_A );
GATE_T_10_I_2: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_10_B );
GATE_T_10_I_3: AND3 port map ( O=>T_10, I0=>p2_6XPIN, I2=>GATE_T_10_A, I1=>GATE_T_10_B );
GATE_T_11_I_1: AND2 port map ( O=>T_11, I1=>p8_6XPIN, I0=>adresse_1XPIN );
GATE_T_12_I_1: AND2 port map ( O=>T_12, I1=>rdPIN, I0=>GATE_T_12_A );
GATE_T_12_I_2: INV port map ( O=>GATE_T_12_A, I0=>wrPIN );
GATE_T_13_I_1: INV port map ( I0=>adresse_0XPIN, O=>GATE_T_13_A );
GATE_T_13_I_2: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_13_B );
GATE_T_13_I_3: AND3 port map ( O=>T_13, I0=>p2_7XPIN, I2=>GATE_T_13_A, I1=>GATE_T_13_B );
GATE_T_14_I_1: AND2 port map ( O=>T_14, I1=>p8_7XPIN, I0=>adresse_1XPIN );
GATE_T_15_I_1: NOR2 port map ( O=>T_15, I1=>adresse_1XPIN, I0=>adresse_2XPIN );
GATE_T_16_I_1: AND2 port map ( O=>T_16, I1=>adresse_3XPIN, I0=>GATE_T_16_A );
GATE_T_16_I_2: INV port map ( O=>GATE_T_16_A, I0=>adresse_4XPIN );
GATE_T_17_I_1: NOR2 port map ( O=>T_17, I1=>csPIN, I0=>adresse_5XPIN );
GATE_T_18_I_1: NOR2 port map ( O=>T_18, I1=>adresse_0XPIN, I0=>adresse_2XPIN );
GATE_T_19_I_1: AND2 port map ( O=>T_19, I1=>adresse_3XPIN, I0=>GATE_T_19_A );
GATE_T_19_I_2: INV port map ( O=>GATE_T_19_A, I0=>adresse_4XPIN );
GATE_T_20_I_1: NOR2 port map ( O=>T_20, I1=>csPIN, I0=>adresse_5XPIN );
GATE_T_21_I_1: AND2 port map ( O=>T_21, I1=>p2_4XPIN, I0=>GATE_T_21_A );
GATE_T_21_I_2: INV port map ( O=>GATE_T_21_A, I0=>adresse_0XPIN );
GATE_T_22_I_1: NOR2 port map ( O=>T_22, I1=>adresse_1XPIN, I0=>adresse_2XPIN );
GATE_T_23_I_1: AND2 port map ( O=>T_23, I1=>adresse_3XPIN, I0=>GATE_T_23_A );
GATE_T_23_I_2: INV port map ( O=>GATE_T_23_A, I0=>adresse_4XPIN );
GATE_T_24_I_1: NOR2 port map ( O=>T_24, I1=>csPIN, I0=>adresse_5XPIN );
GATE_T_25_I_1: AND2 port map ( O=>T_25, I1=>p2_5XPIN, I0=>GATE_T_25_A );
GATE_T_25_I_2: INV port map ( O=>GATE_T_25_A, I0=>adresse_0XPIN );
GATE_T_26_I_1: NOR2 port map ( O=>T_26, I1=>adresse_1XPIN, I0=>adresse_2XPIN );
GATE_T_27_I_1: AND2 port map ( O=>T_27, I1=>adresse_3XPIN, I0=>GATE_T_27_A );
GATE_T_27_I_2: INV port map ( O=>GATE_T_27_A, I0=>adresse_4XPIN );
GATE_T_28_I_1: NOR2 port map ( O=>T_28, I1=>csPIN, I0=>adresse_5XPIN );
end NetList;
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