test_pld_tb.vhd

TQ公司的STK16x开发系统的源码

LIBRARY ieee;
LIBRARY generics;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE generics.components.ALL;

ENTITY Test_PLD_tb IS
END Test_PLD_tb;

ARCHITECTURE behavior OF Test_PLD_tb IS 

	COMPONENT Test_PLD
	PORT(
		adresse : IN std_logic_vector(5 downto 0);
--		clk : IN std_logic;
--		reset : IN std_logic;
		rd : IN std_logic;
		wr : IN std_logic;
		cs : IN std_logic;       
		data : INOUT std_logic_vector(7 downto 0);
		p2 : INOUT std_logic_vector(7 downto 0);
		p7 : INOUT std_logic_vector(3 downto 0);
		p8_6 : INOUT std_logic;
		p8_7 : INOUT std_logic
--		p9_5 : INOUT std_logic
		);
	END COMPONENT;

	SIGNAL adresse :  std_logic_vector(5 downto 0);
--	SIGNAL clk :  std_logic;
	SIGNAL reset :  std_logic;
	SIGNAL rd :  std_logic;
	SIGNAL wr :  std_logic;
	SIGNAL cs :  std_logic;
	SIGNAL data :  std_logic_vector(7 downto 0) := "11001100";
	SIGNAL p2 :  std_logic_vector(7 downto 0);
	SIGNAL p7 :  std_logic_vector(3 downto 0);
	SIGNAL p8_6 :  std_logic;
	SIGNAL p8_7 :  std_logic;
	SIGNAL p9_5 :  std_logic;

BEGIN

	uut: Test_PLD PORT MAP(
		adresse => adresse,
--		clk => clk,
--		reset => reset,
		rd => rd,
		wr => wr,
		cs => cs,
		data => data,
		p2 => p2,
		p7 => p7,
		p8_6 => p8_6,
		p8_7 => p8_7
--		p9_5 => p9_5
	);

process
begin
p8_6 <= '1';
p8_7 <= '0';
p7 <= "0101";
p2 <= "00110011";
wait;
end process;
	
PROCESS
BEGIN
cs <= '1';
rd <= '1';
wr <= '1';
adresse <= "111101";
wait for 100 ns;
cs <= '0';
rd <= '0';
adresse <= "001010";
wait;
END PROCESS;

END;