verilog.properties

来自「porting scintilla to qt」· PROPERTIES 代码 · 共 97 行

# Define SciTE settings for Verilog files.

# Verilog files
file.patterns.verilog=*.v;*.vh
filter.verilog=Verilog (verilog)|$(file.patterns.verilog)|

lexer.$(file.patterns.verilog)=verilog

word.chars.verilog=$(chars.alpha)$(chars.numeric)_`$#
word.characters.$(file.patterns.verilog)=$(word.chars.verilog)

calltip.verilog.word.characters=$(chars.alpha)$(chars.numeric)_$

comment.block.verilog=//~
#comment.block.at.line.start.verilog=1
comment.stream.start.verilog=/*
comment.stream.end.verilog=*/
comment.box.start.verilog=/*
comment.box.middle.verilog= *
comment.box.end.verilog= */

fold.verilog.flags=0

#statement.lookback.$(file.patterns.verilog)=20
#block.start.$(file.patterns.verilog)=5 begin
#block.end.$(file.patterns.verilog)=5 end
#statement.indent.$(file.patterns.verilog)=5 always case casex casez else for if while \
#module function task

indent.maintain.$(file.patterns.verilog)=1;

preprocessor.symbol.$(file.patterns.verilog)=`
preprocessor.start.$(file.patterns.verilog)=ifdef
preprocessor.middle.$(file.patterns.verilog)=else
preprocessor.end.$(file.patterns.verilog)=endif

keywordclass.verilog=always and assign begin \
xbuf buf bufif0 bufif1 case casex casez cmos \
default defparam else end endcase \
endfunction endmodule endprimitive endspecify \
endtable endtask event for force forever \
fork function if initial inout input \
integer join macromodule makefile module \
nand negedge nmos nor not notif0 notif1 \
or output parameter pmos posedge primitive \
pulldown pullup rcmos real realtime reg \
repeat rnmos rpmos rtran rtranif0 rtranif1 \
signed specify specparam supply supply0 supply1 table \
task time tran tranif0 tranif1 tri tri0 \
tri1 triand trior trireg vectored wait \
wand while wire wor xnor xor

keywords.$(file.patterns.verilog)=$(keywordclass.verilog)

keywords3.$(file.patterns.verilog)=$readmemb $readmemh $sreadmemb $sreadmemh $display $write $strobe $monitor $fdisplay $fwrite $fstrobe \
$fmonitor $fopen $fclose $time $stime $realtime $scale $printtimescale $timeformat $stop $finish $save \
$incsave $restart $input $log $nolog $key $nokey $scope $showscopes $showscopes $showvars $showvars \
$countdrivers $list $monitoron $monitoroff $dumpon $dumpoff $dumpfile $dumplimit $dumpflush $dumpvars \
$dumpall $reset $reset $reset $reset $reset $random $getpattern $rtoi $itor $realtobits $bitstoreal \
$setup $hold $setuphold $period $width $skew $recovery
# Verilog styles

# Default
style.verilog.32=$(font.base)
# White space
style.verilog.0=fore:#808080
# Comment
style.verilog.1=$(colour.code.comment.box),$(font.code.comment.box)
# Line Comment
style.verilog.2=$(colour.code.comment.line),$(font.code.comment.line)
# Bang comment
style.verilog.3=fore:#3F7F3F,$(font.code.comment.line),back:#E0F0FF,eolfilled
# Number
style.verilog.4=$(colour.number)
# Keyword
style.verilog.5=$(colour.keyword),bold
# Double quoted string
style.verilog.6=$(colour.string),$(font.string.literal)
# Keyword2
style.verilog.7=fore:#007F7F
# System tasks
style.verilog.8=fore:#804020
# Preprocessor
style.verilog.9=$(colour.preproc)
# Operators
#style.verilog.10=$(colour.operator),bold
style.verilog.10=fore:#007070,bold
# Identifiers
style.verilog.11=
# End of line where string is not closed
style.verilog.12=fore:#000000,$(font.string.literal),back:#E0C0E0,eolfilled
# User defined identifiers and tasks
style.verilog.19=fore:#804020,$(font.code.comment.doc)
# Braces are only matched in operator style
braces.verilog.style=10