📄 orca_cmb.vhd
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------- cell mux41 -----LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.vital_timing.all;ENTITY mux41 IS GENERIC( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "mux41"; tpd_d0_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d1_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d2_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d3_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_sd1_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_sd2_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d2 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d3 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_sd1 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_sd2 : VitalDelayType01 := (0.0 ns, 0.0 ns)); PORT( d0 : IN std_logic; d1 : IN std_logic; d2 : IN std_logic; d3 : IN std_logic; sd1 : IN std_logic; sd2 : IN std_logic; z : OUT std_logic); ATTRIBUTE Vital_Level0 OF mux41 : ENTITY IS TRUE;END mux41;-- architecture body --LIBRARY ieee;USE ieee.vital_primitives.all;ARCHITECTURE v OF mux41 IS ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE; SIGNAL d0_ipd : std_logic := 'X'; SIGNAL d1_ipd : std_logic := 'X'; SIGNAL d2_ipd : std_logic := 'X'; SIGNAL d3_ipd : std_logic := 'X'; SIGNAL sd1_ipd : std_logic := 'X'; SIGNAL sd2_ipd : std_logic := 'X';BEGIN --------------------- -- input path delays --------------------- WireDelay : BLOCK BEGIN VitalWireDelay (d0_ipd, d0, tipd_d0); VitalWireDelay (d1_ipd, d1, tipd_d1); VitalWireDelay (d2_ipd, d2, tipd_d2); VitalWireDelay (d3_ipd, d3, tipd_d3); VitalWireDelay (sd1_ipd, sd1, tipd_sd1); VitalWireDelay (sd2_ipd, sd2, tipd_sd2); END BLOCK; -------------------- -- behavior section -------------------- VitalBehavior : PROCESS (d0_ipd, d1_ipd, d2_ipd, d3_ipd, sd1_ipd, sd2_ipd) -- functionality results VARIABLE results : std_logic_vector(1 to 1) := (others => 'X'); ALIAS z_zd : std_ulogic IS results(1); -- output glitch detection VARIABLEs VARIABLE z_GlitchData : VitalGlitchDataType; BEGIN ------------------------- -- functionality section ------------------------- z_zd := vitalmux (data => (d3_ipd, d2_ipd, d1_ipd, d0_ipd), dselect => (sd2_ipd, sd1_ipd)); ---------------------- -- path delay section ---------------------- VitalPathDelay01 ( OutSignal => z, OutSignalName => "z", OutTemp => z_zd, Paths => (0 => (d0_ipd'last_event, tpd_d0_z, TRUE), 1 => (d1_ipd'last_event, tpd_d1_z, TRUE), 2 => (d2_ipd'last_event, tpd_d2_z, TRUE), 3 => (d3_ipd'last_event, tpd_d3_z, TRUE), 4 => (sd1_ipd'last_event, tpd_sd1_z, TRUE), 5 => (sd2_ipd'last_event, tpd_sd2_z, TRUE)), GlitchData => z_GlitchData, Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);END PROCESS;END v;------- cell mux81 -------LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.vital_timing.all;-- entity declaration --ENTITY mux81 IS GENERIC( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "mux81"; tpd_d0_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d1_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d2_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d3_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d4_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d5_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d6_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d7_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_sd1_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_sd2_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_sd3_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d2 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d3 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d4 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d5 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d6 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d7 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_sd1 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_sd2 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_sd3 : VitalDelayType01 := (0.0 ns, 0.0 ns)); PORT( d0 : IN std_logic; d1 : IN std_logic; d2 : IN std_logic; d3 : IN std_logic; d4 : IN std_logic; d5 : IN std_logic; d6 : IN std_logic; d7 : IN std_logic; sd1 : IN std_logic; sd2 : IN std_logic; sd3 : IN std_logic; z : OUT std_logic); ATTRIBUTE Vital_Level0 OF mux81 : ENTITY IS TRUE;END mux81;-- architecture body --LIBRARY ieee;USE ieee.vital_primitives.all;ARCHITECTURE v OF mux81 IS ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE; SIGNAL d0_ipd : std_logic := 'X'; SIGNAL d1_ipd : std_logic := 'X'; SIGNAL d2_ipd : std_logic := 'X'; SIGNAL d3_ipd : std_logic := 'X'; SIGNAL d4_ipd : std_logic := 'X'; SIGNAL d5_ipd : std_logic := 'X'; SIGNAL d6_ipd : std_logic := 'X'; SIGNAL d7_ipd : std_logic := 'X'; SIGNAL sd1_ipd : std_logic := 'X'; SIGNAL sd2_ipd : std_logic := 'X'; SIGNAL sd3_ipd : std_logic := 'X';BEGIN --------------------- -- input path delays --------------------- WireDelay : BLOCK BEGIN VitalWireDelay (d0_ipd, d0, tipd_d0); VitalWireDelay (d1_ipd, d1, tipd_d1); VitalWireDelay (d2_ipd, d2, tipd_d2); VitalWireDelay (d3_ipd, d3, tipd_d3); VitalWireDelay (d4_ipd, d4, tipd_d4); VitalWireDelay (d5_ipd, d5, tipd_d5); VitalWireDelay (d6_ipd, d6, tipd_d6); VitalWireDelay (d7_ipd, d7, tipd_d7); VitalWireDelay (sd1_ipd, sd1, tipd_sd1); VitalWireDelay (sd2_ipd, sd2, tipd_sd2); VitalWireDelay (sd3_ipd, sd3, tipd_sd3); END BLOCK; -------------------- -- behavior section -------------------- VitalBehavior : PROCESS (d0_ipd, d1_ipd, d2_ipd, d3_ipd, d4_ipd, d5_ipd, d6_ipd, d7_ipd, sd1_ipd, sd2_ipd, sd3_ipd) -- functionality results VARIABLE results : std_logic_vector(1 to 1) := (others => 'X'); ALIAS z_zd : std_ulogic IS results(1); -- output glitch detection VARIABLEs VARIABLE z_GlitchData : VitalGlitchDataType; BEGIN ------------------------- -- functionality section ------------------------- z_zd := vitalmux (data => (d7_ipd, d6_ipd, d5_ipd, d4_ipd, d3_ipd, d2_ipd, d1_ipd, d0_ipd), dselect => (sd3_ipd, sd2_ipd, sd1_ipd)); ---------------------- -- path delay section ---------------------- VitalPathDelay01 ( OutSignal => z, OutSignalName => "z", OutTemp => z_zd, Paths => (0 => (d0_ipd'last_event, tpd_d0_z, TRUE), 1 => (d1_ipd'last_event, tpd_d1_z, TRUE), 2 => (d2_ipd'last_event, tpd_d2_z, TRUE), 3 => (d3_ipd'last_event, tpd_d3_z, TRUE), 4 => (d4_ipd'last_event, tpd_d4_z, TRUE), 5 => (d5_ipd'last_event, tpd_d5_z, TRUE), 6 => (d6_ipd'last_event, tpd_d6_z, TRUE), 7 => (d7_ipd'last_event, tpd_d7_z, TRUE), 8 => (sd1_ipd'last_event, tpd_sd1_z, TRUE), 9 => (sd2_ipd'last_event, tpd_sd2_z, TRUE), 10 => (sd3_ipd'last_event, tpd_sd3_z, TRUE)), GlitchData => z_GlitchData, Mode => OnDetect, XOn => XOn, MsgOn => MsgOn);END PROCESS;END v;------- cell mux161 -------LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.vital_timing.all;-- entity declaration --ENTITY mux161 IS GENERIC( TimingChecksOn : boolean := TRUE; XOn : boolean := FALSE; MsgOn : boolean := TRUE; InstancePath : string := "mux81"; tpd_d0_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d1_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d2_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d3_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d4_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d5_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d6_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d7_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d8_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d9_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d10_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d11_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d12_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d13_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d14_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_d15_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_sd1_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_sd2_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_sd3_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tpd_sd4_z : VitalDelayType01 := (0.01 ns, 0.01 ns); tipd_d0 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d1 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d2 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d3 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d4 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d5 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d6 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d7 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d8 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d9 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d10 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d11 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d12 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d13 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d14 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_d15 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_sd1 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_sd2 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_sd3 : VitalDelayType01 := (0.0 ns, 0.0 ns); tipd_sd4 : VitalDelayType01 := (0.0 ns, 0.0 ns)); PORT( d0 : IN std_logic; d1 : IN std_logic; d2 : IN std_logic; d3 : IN std_logic; d4 : IN std_logic; d5 : IN std_logic; d6 : IN std_logic; d7 : IN std_logic; d8 : IN std_logic; d9 : IN std_logic; d10 : IN std_logic; d11 : IN std_logic; d12 : IN std_logic; d13 : IN std_logic; d14 : IN std_logic; d15 : IN std_logic; sd1 : IN std_logic; sd2 : IN std_logic; sd3 : IN std_logic; sd4 : IN std_logic; z : OUT std_logic); ATTRIBUTE Vital_Level0 OF mux161 : ENTITY IS TRUE;END mux161;-- architecture body --LIBRARY ieee;USE ieee.vital_primitives.all;ARCHITECTURE v OF mux161 IS ATTRIBUTE Vital_Level0 OF v : ARCHITECTURE IS TRUE; SIGNAL d0_ipd : std_logic := 'X'; SIGNAL d1_ipd : std_logic := 'X'; SIGNAL d2_ipd : std_logic := 'X'; SIGNAL d3_ipd : std_logic := 'X'; SIGNAL d4_ipd : std_logic := 'X'; SIGNAL d5_ipd : std_logic := 'X'; SIGNAL d6_ipd : std_logic := 'X'; SIGNAL d7_ipd : std_logic := 'X'; SIGNAL d8_ipd : std_logic := 'X'; SIGNAL d9_ipd : std_logic := 'X'; SIGNAL d10_ipd : std_logic := 'X'; SIGNAL d11_ipd : std_logic := 'X'; SIGNAL d12_ipd : std_logic := 'X'; SIGNAL d13_ipd : std_logic := 'X'; SIGNAL d14_ipd : std_logic := 'X'; SIGNAL d15_ipd : std_logic := 'X'; SIGNAL sd1_ipd : std_logic := 'X'; SIGNAL sd2_ipd : std_logic := 'X'; SIGNAL sd3_ipd : std_logic := 'X'; SIGNAL sd4_ipd : std_logic := 'X';BEGIN --------------------- -- input path delays --------------------- WireDelay : BLOCK BEGIN VitalWireDelay (d0_ipd, d0, tipd_d0); VitalWireDelay (d1_ipd, d1, tipd_d1); VitalWireDelay (d2_ipd, d2, tipd_d2); VitalWireDelay (d3_ipd, d3, tipd_d3); VitalWireDelay (d4_ipd, d4, tipd_d4); VitalWireDelay (d5_ipd, d5, tipd_d5); VitalWireDelay (d6_ipd, d6, tipd_d6); VitalWireDelay (d7_ipd, d7, tipd_d7); VitalWireDelay (d8_ipd, d8, tipd_d8); VitalWireDelay (d9_ipd, d9, tipd_d9); VitalWireDelay (d10_ipd, d10, tipd_d10); VitalWireDelay (d11_ipd, d11, tipd_d11); VitalWireDelay (d12_ipd, d12, tipd_d12); VitalWireDelay (d13_ipd, d13, tipd_d13); VitalWireDelay (d14_ipd, d14, tipd_d14); VitalWireDelay (d15_ipd, d15, tipd_d15); VitalWireDelay (sd1_ipd, sd1, tipd_sd1); VitalWireDelay (sd2_ipd, sd2, tipd_sd2); VitalWireDelay (sd3_ipd, sd3, tipd_sd3); VitalWireDelay (sd4_ipd, sd4, tipd_sd4); END BLOCK; -------------------- -- behavior section -------------------- VitalBehavior : PROCESS (d0_ipd, d1_ipd, d2_ipd, d3_ipd, d4_ipd, d5_ipd, d6_ipd, d7_ipd, d8_ipd, d9_ipd, d10_ipd, d11_ipd, d12_ipd, d13_ipd, d14_ipd, d15_ipd, sd1_ipd, sd2_ipd, sd3_ipd, sd4_ipd) -- functionality results VARIABLE results : std_logic_vector(1 to 1) := (others => 'X'); ALIAS z_zd : std_ulogic IS results(1); -- output glitch detection VARIABLEs VARIABLE z_GlitchData : VitalGlitchDataType;⌨️ 快捷键说明
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