📄 orca_mem.vhd
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-- ---------------------------------------------------------------------- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<-- ---------------------------------------------------------------------- Copyright (c) 2005 by Lattice Semiconductor Corporation-- -------------------------------------------------------------------------- Lattice Semiconductor Corporation-- 5555 NE Moore Court-- Hillsboro, OR 97214-- U.S.A.---- TEL: 1-800-Lattice (USA and Canada)-- 1-408-826-6000 (other locations)---- web: http://www.latticesemi.com/-- email: techsupport@latticesemi.com---- ------------------------------------------------------------------------ Simulation Library File for EC/XP---- $Header: /home/rlp/Orfdry/env_rcs/vhdl/pkg/vhdsclibs/data/orca5mg/src/RCS/ORCA_MEM.vhd,v 1.10 2005/09/23 18:48:54 pradeep Exp $ -- ------- package mem1 -------LIBRARY ieee;USE ieee.std_logic_1164.all;PACKAGE mem1 IS TYPE mem_type_1 IS array (natural range <>) OF std_logic; TYPE mem_type_2 IS array (natural range <>) OF std_logic_vector(1 downto 0); TYPE mem_type_4 IS array (natural range <>) OF std_logic_vector(3 downto 0); function hex2bin_2 (hex: Character) return STD_LOGIC_VECTOR; FUNCTION hex2bin_4 (hex: character) RETURN std_logic_vector; FUNCTION init_ram (hex: string) RETURN mem_type_4; FUNCTION init_ram (hex: string) RETURN mem_type_2; FUNCTION init_ram_1 (hex: string) RETURN mem_type_1;END mem1; PACKAGE BODY mem1 IS FUNCTION init_ram (hex: string) RETURN mem_type_2 IS -- skip 0x OF hex string CONSTANT length : integer := hex'length - 2; VARIABLE result : mem_type_2 (length-1 downto 0); BEGIN FOR i in 0 to length-1 LOOP result (length-1-i) := hex2bin_2 (hex(i+3)); END LOOP; RETURN result; END; function hex2bin_2 (hex: Character) return STD_LOGIC_VECTOR is variable result : STD_LOGIC_VECTOR (1 downto 0); begin case hex is when '0' => result := "00"; when '1' => result := "01"; when '2' => result := "10"; when '3' => result := "11"; when '4' => result := "00"; when '5' => result := "01"; when '6' => result := "10"; when '7' => result := "11"; when '8' => result := "00"; when '9' => result := "01"; when 'A'|'a' => result := "10"; when 'B'|'b' => result := "11"; when 'C'|'c' => result := "00"; when 'D'|'d' => result := "01"; when 'E'|'e' => result := "10"; when 'F'|'f' => result := "11"; when others => null; end case; return result; end; FUNCTION hex2bin_4 (hex: character) RETURN std_logic_vector IS VARIABLE result : std_logic_vector (3 downto 0); BEGIN CASE hex IS WHEN '0' => result := "0000"; WHEN '1' => result := "0001"; WHEN '2' => result := "0010"; WHEN '3' => result := "0011"; WHEN '4' => result := "0100"; WHEN '5' => result := "0101"; WHEN '6' => result := "0110"; WHEN '7' => result := "0111"; WHEN '8' => result := "1000"; WHEN '9' => result := "1001"; WHEN 'A'|'a' => result := "1010"; WHEN 'B'|'b' => result := "1011"; WHEN 'C'|'c' => result := "1100"; WHEN 'D'|'d' => result := "1101"; WHEN 'E'|'e' => result := "1110"; WHEN 'F'|'f' => result := "1111"; WHEN others => NULL; END CASE; RETURN result; END; FUNCTION init_ram (hex: string) RETURN mem_type_4 IS -- skip 0x OF hex string CONSTANT length : integer := hex'length - 2; VARIABLE result : mem_type_4 (length-1 downto 0); BEGIN FOR i in 0 to length-1 LOOP result (length-1-i) := hex2bin_4 (hex(i+3)); END LOOP; RETURN result; END; FUNCTION init_ram_1 (hex: string) RETURN mem_type_1 IS -- skip 0x OF hex string CONSTANT length : integer := hex'length - 2; VARIABLE result : mem_type_1 ((4*length)-1 downto 0); VARIABLE result1 : std_logic_vector((4*length)-1 downto 0); BEGIN FOR i in 0 to length-1 LOOP result1 ((4*(length-i))-1 downto (4*(length-1-i))) := hex2bin_4 (hex(i+3)); FOR j in 0 to 3 LOOP result(((4*length)-1)-j-(4*i)) := result1(((4*length)-1)-j-(4*i)); END LOOP; END LOOP; RETURN result; END;END mem1;------- PACKAGE mem2 -------library IEEE;use IEEE.STD_LOGIC_1164.all; package mem2 is function hex2bin (hex: String) return STD_LOGIC_VECTOR; function hex2bin (hex: Character) return STD_LOGIC_VECTOR;end mem2; package body mem2 is function hex2bin (hex: Character) return STD_LOGIC_VECTOR is variable result : STD_LOGIC_VECTOR (3 downto 0); begin case hex is when '0' => result := "0000"; when '1' => result := "0001"; when '2' => result := "0010"; when '3' => result := "0011"; when '4' => result := "0100"; when '5' => result := "0101"; when '6' => result := "0110"; when '7' => result := "0111"; when '8' => result := "1000"; when '9' => result := "1001"; when 'A'|'a' => result := "1010"; when 'B'|'b' => result := "1011"; when 'C'|'c' => result := "1100"; when 'D'|'d' => result := "1101"; when 'E'|'e' => result := "1110"; when 'F'|'f' => result := "1111"; when others => null; end case; return result; end; function hex2bin (hex: String) return STD_LOGIC_VECTOR is -- skip 0x of hex string constant length : Integer := hex'length - 2; variable result : STD_LOGIC_VECTOR (4*length-1 downto 0); begin for i in 0 to length-1 loop result ((length-i)*4-1 downto (length-i-1)*4) := hex2bin(hex(i+3)); end loop; return result; end; end mem2;------- package mem3 -------LIBRARY ieee;USE ieee.std_logic_1164.all;use ieee.std_logic_arith.all;PACKAGE mem3 IS TYPE mem_type_5 IS array (Integer range <>) OF std_logic_vector(17 downto 0); TYPE mem_type_6 IS array (Integer range <>) OF std_logic_vector(15 downto 0); FUNCTION hex2bin (hex: character) RETURN std_logic_vector; FUNCTION str3_slv12 (hex: string) RETURN std_logic_vector; FUNCTION data2data (data_w: integer) RETURN integer; FUNCTION data2addr_w (data_w: integer) RETURN integer; FUNCTION data2data_w (data_w: integer) RETURN integer; FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector; FUNCTION init_ram1 (hex: string) RETURN mem_type_6; FUNCTION str2slv (str: in string) RETURN std_logic_vector; FUNCTION Valid_Address (IN_ADDR : in std_logic_vector) return boolean;END mem3;PACKAGE BODY mem3 IS FUNCTION hex2bin (hex: character) RETURN std_logic_vector IS VARIABLE result : std_logic_vector (3 downto 0); BEGIN CASE hex IS WHEN '0' => result := "0000"; WHEN '1' => result := "0001"; WHEN '2' => result := "0010"; WHEN '3' => result := "0011"; WHEN '4' => result := "0100"; WHEN '5' => result := "0101"; WHEN '6' => result := "0110"; WHEN '7' => result := "0111"; WHEN '8' => result := "1000"; WHEN '9' => result := "1001"; WHEN 'A'|'a' => result := "1010"; WHEN 'B'|'b' => result := "1011"; WHEN 'C'|'c' => result := "1100"; WHEN 'D'|'d' => result := "1101"; WHEN 'E'|'e' => result := "1110"; WHEN 'F'|'f' => result := "1111"; WHEN 'X'|'x' => result := "XXXX"; WHEN others => NULL; END CASE; RETURN result; END; FUNCTION str5_slv18 (s : string(5 downto 1)) return std_logic_vector is VARIABLE result : std_logic_vector(17 downto 0); BEGIN FOR i in 0 to 3 LOOP result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1)); END LOOP; result(17 downto 16) := hex2bin(s(5))(1 downto 0); RETURN result; END; FUNCTION str4_slv16 (s : string(4 downto 1)) return std_logic_vector is VARIABLE result : std_logic_vector(15 downto 0); BEGIN FOR i in 0 to 3 LOOP result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1)); END LOOP; RETURN result; END; FUNCTION str3_slv12 (hex: string) return std_logic_vector is VARIABLE result : std_logic_vector(11 downto 0); BEGIN FOR i in 0 to 2 LOOP result(((i+1)*4)-1 downto (i*4)) := hex2bin(hex(i+1)); END LOOP; RETURN result; END; FUNCTION data2addr_w (data_w : integer) return integer is VARIABLE result : integer; BEGIN CASE data_w IS WHEN 1 => result := 13; WHEN 2 => result := 12; WHEN 4 => result := 11; WHEN 9 => result := 10; WHEN 18 => result := 9; WHEN 36 => result := 8; WHEN others => NULL; END CASE; RETURN result; END; FUNCTION data2data_w (data_w : integer) return integer is VARIABLE result : integer; BEGIN CASE data_w IS WHEN 1 => result := 1; WHEN 2 => result := 2; WHEN 4 => result := 4; WHEN 9 => result := 9; WHEN 18 => result := 18; WHEN 36 => result := 18; WHEN others => NULL; END CASE; RETURN result; END; FUNCTION data2data (data_w : integer) return integer is VARIABLE result : integer; BEGIN CASE data_w IS WHEN 1 => result := 8; WHEN 2 => result := 4; WHEN 4 => result := 2;
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