xuanze.vhd

能自动记时

Library ieee;          --输入选择模块
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity xuanze is
   Port(clk,reset,set:in std_logic;
        en:in std_logic_vector(1 downto 0); 
        a0,a1,a2,a3,a4,a5,a6:in std_logic_vector(3 downto 0);   --公共输入端口
        b0,b1,b2,b3,b4,b5,b6:out std_logic_vector(3 downto 0);  --输出端口B，接计时模块输入端口
        c0,c1,c2,c3,c4,c5,c6:out std_logic_vector(3 downto 0)); --输出端口A，接日期模块输入端口 
End;
Architecture one of xuanze is
begin
process(clk,reset,set)
begin
   if en="00" then 
     b0<=a0;b1<=a1;b2<=a2;b3<=a3;b4<=a4;b5<=a4;b6<=a6;    --使能EN=00,输出接计时模块，显示计时
    elsif  en="11" then
     c0<=a0;c1<=a1;c2<=a2;c3<=a3;c4<=a4;c5<=a5;c6<=a6;    --使能EN=11，输出接日期模块，显示日期
   end if;
end process;
end;