📄 xuanze.rpt
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# a62 & en0 & en1;
-- Node name is ':579'
-- Equation name is '_LC3_A20', type is buried
_LC3_A20 = LCELL( _EQ027);
_EQ027 = !en1 & _LC3_A20
# !en0 & _LC3_A20
# a61 & en0 & en1;
-- Node name is ':588'
-- Equation name is '_LC4_A20', type is buried
_LC4_A20 = LCELL( _EQ028);
_EQ028 = !en1 & _LC4_A20
# !en0 & _LC4_A20
# a60 & en0 & en1;
-- Node name is ':597'
-- Equation name is '_LC2_A3', type is buried
_LC2_A3 = LCELL( _EQ029);
_EQ029 = en1 & _LC2_A3
# en0 & _LC2_A3
# a03 & !en0 & !en1;
-- Node name is ':606'
-- Equation name is '_LC4_A3', type is buried
_LC4_A3 = LCELL( _EQ030);
_EQ030 = en1 & _LC4_A3
# en0 & _LC4_A3
# a02 & !en0 & !en1;
-- Node name is ':615'
-- Equation name is '_LC6_A3', type is buried
_LC6_A3 = LCELL( _EQ031);
_EQ031 = en1 & _LC6_A3
# en0 & _LC6_A3
# a01 & !en0 & !en1;
-- Node name is ':624'
-- Equation name is '_LC7_A3', type is buried
_LC7_A3 = LCELL( _EQ032);
_EQ032 = en1 & _LC7_A3
# en0 & _LC7_A3
# a00 & !en0 & !en1;
-- Node name is ':633'
-- Equation name is '_LC1_A7', type is buried
_LC1_A7 = LCELL( _EQ033);
_EQ033 = en1 & _LC1_A7
# en0 & _LC1_A7
# a13 & !en0 & !en1;
-- Node name is ':642'
-- Equation name is '_LC6_A7', type is buried
_LC6_A7 = LCELL( _EQ034);
_EQ034 = en1 & _LC6_A7
# en0 & _LC6_A7
# a12 & !en0 & !en1;
-- Node name is ':651'
-- Equation name is '_LC4_A7', type is buried
_LC4_A7 = LCELL( _EQ035);
_EQ035 = en1 & _LC4_A7
# en0 & _LC4_A7
# a11 & !en0 & !en1;
-- Node name is ':660'
-- Equation name is '_LC5_A7', type is buried
_LC5_A7 = LCELL( _EQ036);
_EQ036 = en1 & _LC5_A7
# en0 & _LC5_A7
# a10 & !en0 & !en1;
-- Node name is ':669'
-- Equation name is '_LC4_B6', type is buried
_LC4_B6 = LCELL( _EQ037);
_EQ037 = en1 & _LC4_B6
# en0 & _LC4_B6
# a23 & !en0 & !en1;
-- Node name is ':678'
-- Equation name is '_LC5_B6', type is buried
_LC5_B6 = LCELL( _EQ038);
_EQ038 = en1 & _LC5_B6
# en0 & _LC5_B6
# a22 & !en0 & !en1;
-- Node name is ':687'
-- Equation name is '_LC1_B6', type is buried
_LC1_B6 = LCELL( _EQ039);
_EQ039 = en1 & _LC1_B6
# en0 & _LC1_B6
# a21 & !en0 & !en1;
-- Node name is ':696'
-- Equation name is '_LC6_B6', type is buried
_LC6_B6 = LCELL( _EQ040);
_EQ040 = en1 & _LC6_B6
# en0 & _LC6_B6
# a20 & !en0 & !en1;
-- Node name is ':705'
-- Equation name is '_LC3_C24', type is buried
_LC3_C24 = LCELL( _EQ041);
_EQ041 = en1 & _LC3_C24
# en0 & _LC3_C24
# a33 & !en0 & !en1;
-- Node name is ':714'
-- Equation name is '_LC4_C12', type is buried
_LC4_C12 = LCELL( _EQ042);
_EQ042 = en1 & _LC4_C12
# en0 & _LC4_C12
# a32 & !en0 & !en1;
-- Node name is ':723'
-- Equation name is '_LC8_C24', type is buried
_LC8_C24 = LCELL( _EQ043);
_EQ043 = en1 & _LC8_C24
# en0 & _LC8_C24
# a31 & !en0 & !en1;
-- Node name is ':732'
-- Equation name is '_LC5_B13', type is buried
_LC5_B13 = LCELL( _EQ044);
_EQ044 = en1 & _LC5_B13
# en0 & _LC5_B13
# a30 & !en0 & !en1;
-- Node name is ':741'
-- Equation name is '_LC8_C12', type is buried
_LC8_C12 = LCELL( _EQ045);
_EQ045 = en1 & _LC8_C12
# en0 & _LC8_C12
# a43 & !en0 & !en1;
-- Node name is ':750'
-- Equation name is '_LC3_C12', type is buried
_LC3_C12 = LCELL( _EQ046);
_EQ046 = en1 & _LC3_C12
# en0 & _LC3_C12
# a42 & !en0 & !en1;
-- Node name is ':759'
-- Equation name is '_LC1_C24', type is buried
_LC1_C24 = LCELL( _EQ047);
_EQ047 = en1 & _LC1_C24
# en0 & _LC1_C24
# a41 & !en0 & !en1;
-- Node name is ':768'
-- Equation name is '_LC8_B13', type is buried
_LC8_B13 = LCELL( _EQ048);
_EQ048 = en1 & _LC8_B13
# en0 & _LC8_B13
# a40 & !en0 & !en1;
-- Node name is ':777'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = LCELL( _EQ049);
_EQ049 = a43 & !en0 & !en1
# en1 & _LC1_C12
# en0 & _LC1_C12;
-- Node name is ':786'
-- Equation name is '_LC7_C12', type is buried
_LC7_C12 = LCELL( _EQ050);
_EQ050 = a42 & !en0 & !en1
# en1 & _LC7_C12
# en0 & _LC7_C12;
-- Node name is ':795'
-- Equation name is '_LC2_C24', type is buried
_LC2_C24 = LCELL( _EQ051);
_EQ051 = a41 & !en0 & !en1
# en1 & _LC2_C24
# en0 & _LC2_C24;
-- Node name is ':804'
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = LCELL( _EQ052);
_EQ052 = a40 & !en0 & !en1
# en1 & _LC1_B13
# en0 & _LC1_B13;
-- Node name is ':813'
-- Equation name is '_LC5_A20', type is buried
_LC5_A20 = LCELL( _EQ053);
_EQ053 = en1 & _LC5_A20
# en0 & _LC5_A20
# a63 & !en0 & !en1;
-- Node name is ':822'
-- Equation name is '_LC1_A20', type is buried
_LC1_A20 = LCELL( _EQ054);
_EQ054 = en1 & _LC1_A20
# en0 & _LC1_A20
# a62 & !en0 & !en1;
-- Node name is ':831'
-- Equation name is '_LC2_A20', type is buried
_LC2_A20 = LCELL( _EQ055);
_EQ055 = en1 & _LC2_A20
# en0 & _LC2_A20
# a61 & !en0 & !en1;
-- Node name is ':840'
-- Equation name is '_LC6_A20', type is buried
_LC6_A20 = LCELL( _EQ056);
_EQ056 = en1 & _LC6_A20
# en0 & _LC6_A20
# a60 & !en0 & !en1;
Project Information c:\clock\xuanze.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,125K
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