📄 xuanze.rpt
字号:
63 - - - 11 OUTPUT 0 1 0 0 b52
83 - - C -- OUTPUT 0 1 0 0 b53
136 - - - 19 OUTPUT 0 1 0 0 b60
137 - - - 19 OUTPUT 0 1 0 0 b61
41 - - - 20 OUTPUT 0 1 0 0 b62
11 - - A -- OUTPUT 0 1 0 0 b63
9 - - A -- OUTPUT 0 1 0 0 c00
72 - - - 04 OUTPUT 0 1 0 0 c01
98 - - A -- OUTPUT 0 1 0 0 c02
102 - - A -- OUTPUT 0 1 0 0 c03
118 - - - 07 OUTPUT 0 1 0 0 c10
119 - - - 08 OUTPUT 0 1 0 0 c11
96 - - A -- OUTPUT 0 1 0 0 c12
95 - - A -- OUTPUT 0 1 0 0 c13
69 - - - 06 OUTPUT 0 1 0 0 c20
70 - - - 05 OUTPUT 0 1 0 0 c21
91 - - B -- OUTPUT 0 1 0 0 c22
86 - - B -- OUTPUT 0 1 0 0 c23
128 - - - 13 OUTPUT 0 1 0 0 c30
29 - - C -- OUTPUT 0 1 0 0 c31
79 - - C -- OUTPUT 0 1 0 0 c32
36 - - - 24 OUTPUT 0 1 0 0 c33
49 - - - 14 OUTPUT 0 1 0 0 c40
144 - - - 24 OUTPUT 0 1 0 0 c41
81 - - C -- OUTPUT 0 1 0 0 c42
78 - - C -- OUTPUT 0 1 0 0 c43
23 - - B -- OUTPUT 0 1 0 0 c50
18 - - B -- OUTPUT 0 1 0 0 c51
142 - - - 23 OUTPUT 0 1 0 0 c52
19 - - B -- OUTPUT 0 1 0 0 c53
42 - - - 19 OUTPUT 0 1 0 0 c60
138 - - - 20 OUTPUT 0 1 0 0 c61
13 - - A -- OUTPUT 0 1 0 0 c62
14 - - A -- OUTPUT 0 1 0 0 c63
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\clock\xuanze.rpt
xuanze
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 03 OR2 3 0 1 0 :345
- 5 - A 03 OR2 3 0 1 0 :354
- 8 - A 03 OR2 3 0 1 0 :363
- 3 - A 03 OR2 3 0 1 0 :372
- 8 - A 07 OR2 3 0 1 0 :381
- 7 - A 07 OR2 3 0 1 0 :390
- 2 - A 07 OR2 3 0 1 0 :399
- 3 - A 07 OR2 3 0 1 0 :408
- 7 - B 06 OR2 3 0 1 0 :417
- 2 - B 06 OR2 3 0 1 0 :426
- 8 - B 06 OR2 3 0 1 0 :435
- 3 - B 06 OR2 3 0 1 0 :444
- 7 - C 24 OR2 3 0 1 0 :453
- 5 - C 12 OR2 3 0 1 0 :462
- 4 - C 24 OR2 3 0 1 0 :471
- 4 - B 13 OR2 3 0 1 0 :480
- 6 - C 12 OR2 3 0 1 0 :489
- 2 - C 12 OR2 3 0 1 0 :498
- 5 - C 24 OR2 3 0 1 0 :507
- 6 - B 13 OR2 3 0 1 0 :516
- 3 - B 13 OR2 3 0 1 0 :525
- 6 - C 24 OR2 3 0 1 0 :534
- 2 - B 13 OR2 3 0 1 0 :543
- 7 - B 13 OR2 3 0 1 0 :552
- 8 - A 20 OR2 3 0 1 0 :561
- 7 - A 20 OR2 3 0 1 0 :570
- 3 - A 20 OR2 3 0 1 0 :579
- 4 - A 20 OR2 3 0 1 0 :588
- 2 - A 03 OR2 3 0 1 0 :597
- 4 - A 03 OR2 3 0 1 0 :606
- 6 - A 03 OR2 3 0 1 0 :615
- 7 - A 03 OR2 3 0 1 0 :624
- 1 - A 07 OR2 3 0 1 0 :633
- 6 - A 07 OR2 3 0 1 0 :642
- 4 - A 07 OR2 3 0 1 0 :651
- 5 - A 07 OR2 3 0 1 0 :660
- 4 - B 06 OR2 3 0 1 0 :669
- 5 - B 06 OR2 3 0 1 0 :678
- 1 - B 06 OR2 3 0 1 0 :687
- 6 - B 06 OR2 3 0 1 0 :696
- 3 - C 24 OR2 3 0 1 0 :705
- 4 - C 12 OR2 3 0 1 0 :714
- 8 - C 24 OR2 3 0 1 0 :723
- 5 - B 13 OR2 3 0 1 0 :732
- 8 - C 12 OR2 3 0 1 0 :741
- 3 - C 12 OR2 3 0 1 0 :750
- 1 - C 24 OR2 3 0 1 0 :759
- 8 - B 13 OR2 3 0 1 0 :768
- 1 - C 12 OR2 3 0 1 0 :777
- 7 - C 12 OR2 3 0 1 0 :786
- 2 - C 24 OR2 3 0 1 0 :795
- 1 - B 13 OR2 3 0 1 0 :804
- 5 - A 20 OR2 3 0 1 0 :813
- 1 - A 20 OR2 3 0 1 0 :822
- 2 - A 20 OR2 3 0 1 0 :831
- 6 - A 20 OR2 3 0 1 0 :840
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\clock\xuanze.rpt
xuanze
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 10/ 48( 20%) 3/ 48( 6%) 1/16( 6%) 11/16( 68%) 0/16( 0%)
B: 2/ 96( 2%) 7/ 48( 14%) 9/ 48( 18%) 2/16( 12%) 9/16( 56%) 0/16( 0%)
C: 3/ 96( 3%) 7/ 48( 14%) 6/ 48( 12%) 2/16( 12%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
05: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
09: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
12: 4/24( 16%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
19: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\clock\xuanze.rpt
xuanze
** EQUATIONS **
a00 : INPUT;
a01 : INPUT;
a02 : INPUT;
a03 : INPUT;
a10 : INPUT;
a11 : INPUT;
a12 : INPUT;
a13 : INPUT;
a20 : INPUT;
a21 : INPUT;
a22 : INPUT;
a23 : INPUT;
a30 : INPUT;
a31 : INPUT;
a32 : INPUT;
a33 : INPUT;
a40 : INPUT;
a41 : INPUT;
a42 : INPUT;
a43 : INPUT;
a50 : INPUT;
a51 : INPUT;
a52 : INPUT;
a53 : INPUT;
a60 : INPUT;
a61 : INPUT;
a62 : INPUT;
a63 : INPUT;
en0 : INPUT;
en1 : INPUT;
-- Node name is 'b00'
-- Equation name is 'b00', type is output
b00 = _LC7_A3;
-- Node name is 'b01'
-- Equation name is 'b01', type is output
b01 = _LC6_A3;
-- Node name is 'b02'
-- Equation name is 'b02', type is output
b02 = _LC4_A3;
-- Node name is 'b03'
-- Equation name is 'b03', type is output
b03 = _LC2_A3;
-- Node name is 'b10'
-- Equation name is 'b10', type is output
b10 = _LC5_A7;
-- Node name is 'b11'
-- Equation name is 'b11', type is output
b11 = _LC4_A7;
-- Node name is 'b12'
-- Equation name is 'b12', type is output
b12 = _LC6_A7;
-- Node name is 'b13'
-- Equation name is 'b13', type is output
b13 = _LC1_A7;
-- Node name is 'b20'
-- Equation name is 'b20', type is output
b20 = _LC6_B6;
-- Node name is 'b21'
-- Equation name is 'b21', type is output
b21 = _LC1_B6;
-- Node name is 'b22'
-- Equation name is 'b22', type is output
b22 = _LC5_B6;
-- Node name is 'b23'
-- Equation name is 'b23', type is output
b23 = _LC4_B6;
-- Node name is 'b30'
-- Equation name is 'b30', type is output
b30 = _LC5_B13;
-- Node name is 'b31'
-- Equation name is 'b31', type is output
b31 = _LC8_C24;
-- Node name is 'b32'
-- Equation name is 'b32', type is output
b32 = _LC4_C12;
-- Node name is 'b33'
-- Equation name is 'b33', type is output
b33 = _LC3_C24;
-- Node name is 'b40'
-- Equation name is 'b40', type is output
b40 = _LC8_B13;
-- Node name is 'b41'
-- Equation name is 'b41', type is output
b41 = _LC1_C24;
-- Node name is 'b42'
-- Equation name is 'b42', type is output
b42 = _LC3_C12;
-- Node name is 'b43'
-- Equation name is 'b43', type is output
b43 = _LC8_C12;
-- Node name is 'b50'
-- Equation name is 'b50', type is output
b50 = _LC1_B13;
-- Node name is 'b51'
-- Equation name is 'b51', type is output
b51 = _LC2_C24;
-- Node name is 'b52'
-- Equation name is 'b52', type is output
b52 = _LC7_C12;
-- Node name is 'b53'
-- Equation name is 'b53', type is output
b53 = _LC1_C12;
-- Node name is 'b60'
-- Equation name is 'b60', type is output
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