week1.vhd

来自「能自动记时」· VHDL 代码 · 共 23 行

Library ieee;              --星期模块
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity week1 is
   Port(clkday,set,reset:in std_logic;
                      w1:in std_logic_vector(3 downto 0);   --输入预置星期几     
                    week:buffer std_logic_vector(3 downto 0));  --输出星期几显示
end week1;
Architecture one of week1 is
Begin
Process(clkday,reset,set,w1)
  variable  cq1: STD_LOGIC_vector( 3 downto 0);
Begin
  if reset='1' then cq1:="0000";  
     Elsif clkday'event and clkday='1' then  cq1:=cq1+1;  
       if cq1="1000" then cq1:="0001";              --星期满7，返回重复计数
       end if;
   end if;
   week<=cq1;
End process;
end one;