📄 riqi.rpt
字号:
55 - - C -- OUTPUT 0 1 0 0 YEAR03
19 - - C -- OUTPUT 0 1 0 0 YEAR10
21 - - C -- OUTPUT 0 1 0 0 YEAR11
20 - - C -- OUTPUT 0 1 0 0 YEAR12
22 - - C -- OUTPUT 0 1 0 0 YEAR13
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\clock\riqi.rpt
riqi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - A 12 AND2 0 3 0 2 |DAY1:5|LPM_ADD_SUB:144|addcore:adder|:55
- 2 - A 07 DFFE + 0 2 0 9 |DAY1:5|:20
- 7 - A 12 DFFE + 0 3 1 1 |DAY1:5|cq13 (|DAY1:5|:24)
- 4 - A 12 DFFE + 0 2 1 2 |DAY1:5|cq12 (|DAY1:5|:25)
- 5 - A 12 DFFE + 0 3 1 2 |DAY1:5|cq11 (|DAY1:5|:26)
- 2 - A 12 DFFE + 0 2 1 3 |DAY1:5|cq10 (|DAY1:5|:27)
- 8 - A 07 DFFE + 0 3 1 2 |DAY1:5|cq03 (|DAY1:5|:28)
- 6 - A 07 DFFE + 0 2 1 3 |DAY1:5|cq02 (|DAY1:5|:29)
- 7 - A 07 DFFE + 0 3 1 4 |DAY1:5|cq01 (|DAY1:5|:30)
- 1 - A 12 DFFE + ! 0 2 1 5 |DAY1:5|cq00 (|DAY1:5|:31)
- 6 - A 12 OR2 s ! 0 3 0 1 |DAY1:5|~69~1
- 3 - A 12 OR2 ! 0 4 0 6 |DAY1:5|:69
- 5 - A 07 OR2 s ! 0 3 0 1 |DAY1:5|~135~1
- 3 - A 07 AND2 0 4 0 6 |DAY1:5|:135
- 6 - A 17 AND2 0 2 0 1 |MONTH1:2|LPM_ADD_SUB:156|addcore:adder|:55
- 1 - A 07 DFFE 0 3 0 8 |MONTH1:2|:20
- 5 - A 17 DFFE 0 4 1 1 |MONTH1:2|cq13 (|MONTH1:2|:24)
- 2 - A 17 DFFE 0 4 1 2 |MONTH1:2|cq12 (|MONTH1:2|:25)
- 3 - A 17 DFFE 0 3 1 3 |MONTH1:2|cq11 (|MONTH1:2|:26)
- 1 - A 17 DFFE 0 3 1 4 |MONTH1:2|cq10 (|MONTH1:2|:27)
- 4 - A 18 DFFE 0 4 1 3 |MONTH1:2|cq03 (|MONTH1:2|:28)
- 6 - A 18 DFFE 0 4 1 3 |MONTH1:2|cq02 (|MONTH1:2|:29)
- 3 - A 18 DFFE 0 4 1 4 |MONTH1:2|cq01 (|MONTH1:2|:30)
- 8 - A 18 DFFE ! 0 2 1 5 |MONTH1:2|cq00 (|MONTH1:2|:31)
- 4 - A 17 OR2 s ! 0 3 0 1 |MONTH1:2|~65~1
- 2 - A 18 OR2 s ! 0 3 0 1 |MONTH1:2|~65~2
- 8 - A 17 OR2 ! 0 4 0 3 |MONTH1:2|:65
- 7 - A 18 OR2 ! 0 4 0 6 |MONTH1:2|:130
- 4 - A 07 SOFT s ! 1 0 0 2 RESET~1
- 8 - B 09 DFFE + 0 3 1 1 |WEEK1:25|cq13 (|WEEK1:25|:14)
- 2 - B 09 DFFE + 0 2 1 2 |WEEK1:25|cq12 (|WEEK1:25|:15)
- 1 - B 09 DFFE + 0 1 1 3 |WEEK1:25|cq11 (|WEEK1:25|:16)
- 4 - B 09 DFFE + 0 3 1 3 |WEEK1:25|cq10 (|WEEK1:25|:17)
- 5 - C 14 AND2 0 2 0 1 |YEAR1:4|LPM_ADD_SUB:59|addcore:adder|:55
- 6 - C 14 OR2 0 4 0 1 |YEAR1:4|LPM_ADD_SUB:59|addcore:adder|:69
- 8 - C 14 DFFE 0 4 1 2 |YEAR1:4|cq13 (|YEAR1:4|:22)
- 2 - C 14 DFFE 0 4 1 2 |YEAR1:4|cq12 (|YEAR1:4|:23)
- 3 - C 14 DFFE 0 4 1 3 |YEAR1:4|cq11 (|YEAR1:4|:24)
- 1 - C 14 DFFE 0 2 1 4 |YEAR1:4|cq10 (|YEAR1:4|:25)
- 6 - C 06 DFFE 0 4 1 2 |YEAR1:4|cq03 (|YEAR1:4|:26)
- 1 - C 06 DFFE 0 3 1 3 |YEAR1:4|cq02 (|YEAR1:4|:27)
- 2 - C 06 DFFE 0 4 1 3 |YEAR1:4|cq01 (|YEAR1:4|:28)
- 5 - C 06 DFFE 0 1 1 4 |YEAR1:4|cq00 (|YEAR1:4|:29)
- 3 - C 06 AND2 0 4 0 4 |YEAR1:4|:45
- 4 - C 14 OR2 ! 0 4 0 3 |YEAR1:4|:60
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\clock\riqi.rpt
riqi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 12/ 96( 12%) 3/ 48( 6%) 3/ 48( 6%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 1/ 96( 1%) 3/ 48( 6%) 2/ 48( 4%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
C: 3/ 96( 3%) 3/ 48( 6%) 4/ 48( 8%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\clock\riqi.rpt
riqi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 13 CLKD
DFF 9 |DAY1:5|:20
DFF 8 |MONTH1:2|:20
Device-Specific Information: c:\clock\riqi.rpt
riqi
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 29 RESET
Device-Specific Information: c:\clock\riqi.rpt
riqi
** EQUATIONS **
CLKD : INPUT;
RESET : INPUT;
-- Node name is 'DA00'
-- Equation name is 'DA00', type is output
DA00 = _LC1_A12;
-- Node name is 'DA01'
-- Equation name is 'DA01', type is output
DA01 = _LC7_A7;
-- Node name is 'DA02'
-- Equation name is 'DA02', type is output
DA02 = _LC6_A7;
-- Node name is 'DA03'
-- Equation name is 'DA03', type is output
DA03 = _LC8_A7;
-- Node name is 'DA10'
-- Equation name is 'DA10', type is output
DA10 = _LC2_A12;
-- Node name is 'DA11'
-- Equation name is 'DA11', type is output
DA11 = _LC5_A12;
-- Node name is 'DA12'
-- Equation name is 'DA12', type is output
DA12 = _LC4_A12;
-- Node name is 'DA13'
-- Equation name is 'DA13', type is output
DA13 = _LC7_A12;
-- Node name is 'MONTH00'
-- Equation name is 'MONTH00', type is output
MONTH00 = _LC8_A18;
-- Node name is 'MONTH01'
-- Equation name is 'MONTH01', type is output
MONTH01 = _LC3_A18;
-- Node name is 'MONTH02'
-- Equation name is 'MONTH02', type is output
MONTH02 = _LC6_A18;
-- Node name is 'MONTH03'
-- Equation name is 'MONTH03', type is output
MONTH03 = _LC4_A18;
-- Node name is 'MONTH10'
-- Equation name is 'MONTH10', type is output
MONTH10 = _LC1_A17;
-- Node name is 'MONTH11'
-- Equation name is 'MONTH11', type is output
MONTH11 = _LC3_A17;
-- Node name is 'MONTH12'
-- Equation name is 'MONTH12', type is output
MONTH12 = _LC2_A17;
-- Node name is 'MONTH13'
-- Equation name is 'MONTH13', type is output
MONTH13 = _LC5_A17;
-- Node name is 'RESET~1'
-- Equation name is 'RESET~1', location is LC4_A7, type is buried.
-- synthesized logic cell
!_LC4_A7 = _LC4_A7~NOT;
_LC4_A7~NOT = LCELL(!RESET);
-- Node name is 'WEEK0'
-- Equation name is 'WEEK0', type is output
WEEK0 = _LC4_B9;
-- Node name is 'WEEK1'
-- Equation name is 'WEEK1', type is output
WEEK1 = _LC1_B9;
-- Node name is 'WEEK2'
-- Equation name is 'WEEK2', type is output
WEEK2 = _LC2_B9;
-- Node name is 'WEEK3'
-- Equation name is 'WEEK3', type is output
WEEK3 = _LC8_B9;
-- Node name is 'YEAR00'
-- Equation name is 'YEAR00', type is output
YEAR00 = _LC5_C6;
-- Node name is 'YEAR01'
-- Equation name is 'YEAR01', type is output
YEAR01 = _LC2_C6;
-- Node name is 'YEAR02'
-- Equation name is 'YEAR02', type is output
YEAR02 = _LC1_C6;
-- Node name is 'YEAR03'
-- Equation name is 'YEAR03', type is output
YEAR03 = _LC6_C6;
-- Node name is 'YEAR10'
-- Equation name is 'YEAR10', type is output
YEAR10 = _LC1_C14;
-- Node name is 'YEAR11'
-- Equation name is 'YEAR11', type is output
YEAR11 = _LC3_C14;
-- Node name is 'YEAR12'
-- Equation name is 'YEAR12', type is output
YEAR12 = _LC2_C14;
-- Node name is 'YEAR13'
-- Equation name is 'YEAR13', type is output
YEAR13 = _LC8_C14;
-- Node name is '|DAY1:5|:31' = '|DAY1:5|cq00'
-- Equation name is '_LC1_A12', type is buried
!_LC1_A12 = _LC1_A12~NOT;
_LC1_A12~NOT = DFFE( _EQ001, GLOBAL( CLKD), GLOBAL(!RESET), VCC, VCC);
_EQ001 = _LC3_A7
# _LC1_A12 & !_LC3_A12;
-- Node name is '|DAY1:5|:30' = '|DAY1:5|cq01'
-- Equation name is '_LC7_A7', type is buried
_LC7_A7 = DFFE( _EQ002, GLOBAL( CLKD), GLOBAL(!RESET), VCC, VCC);
_EQ002 = !_LC1_A12 & !_LC3_A7 & _LC7_A7
# !_LC3_A7 & _LC3_A12 & _LC7_A7
# _LC1_A12 & !_LC3_A7 & !_LC3_A12 & !_LC7_A7;
-- Node name is '|DAY1:5|:29' = '|DAY1:5|cq02'
-- Equation name is '_LC6_A7', type is buried
_LC6_A7 = DFFE( _EQ003, GLOBAL( CLKD), GLOBAL(!RESET), VCC, VCC);
_EQ003 = _LC6_A7 & !_LC7_A7
# !_LC1_A12 & _LC6_A7
# _LC1_A12 & !_LC6_A7 & _LC7_A7;
-- Node name is '|DAY1:5|:28' = '|DAY1:5|cq03'
-- Equation name is '_LC8_A7', type is buried
_LC8_A7 = DFFE( _EQ004, GLOBAL( CLKD), GLOBAL(!RESET), VCC, VCC);
_EQ004 = !_LC1_A12 & _LC8_A7
# _LC1_A12 & _LC6_A7 & _LC7_A7 & !_LC8_A7
# _LC6_A7 & !_LC7_A7 & _LC8_A7
# !_LC6_A7 & _LC7_A7 & _LC8_A7;
-- Node name is '|DAY1:5|:27' = '|DAY1:5|cq10'
-- Equation name is '_LC2_A12', type is buried
_LC2_A12 = DFFE( _EQ005, GLOBAL( CLKD), GLOBAL(!RESET), VCC, VCC);
_EQ005 = _LC2_A12 & !_LC3_A7 & !_LC3_A12
# !_LC2_A12 & _LC3_A7;
-- Node name is '|DAY1:5|:26' = '|DAY1:5|cq11'
-- Equation name is '_LC5_A12', type is buried
_LC5_A12 = DFFE( _EQ006, GLOBAL( CLKD), GLOBAL(!RESET), VCC, VCC);
_EQ006 = !_LC3_A7 & !_LC3_A12 & _LC5_A12
# !_LC2_A12 & _LC3_A7 & _LC5_A12
# _LC2_A12 & _LC3_A7 & !_LC5_A12;
-- Node name is '|DAY1:5|:25' = '|DAY1:5|cq12'
-- Equation name is '_LC4_A12', type is buried
_LC4_A12 = DFFE( _EQ007, GLOBAL( CLKD), GLOBAL(!RESET), VCC, VCC);
_EQ007 = _LC4_A12 & !_LC8_A12
# _LC3_A7 & !_LC4_A12 & _LC8_A12
# !_LC3_A7 & _LC4_A12;
-- Node name is '|DAY1:5|:24' = '|DAY1:5|cq13'
-- Equation name is '_LC7_A12', type is buried
_LC7_A12 = DFFE( _EQ008, GLOBAL( CLKD), GLOBAL(!RESET), VCC, VCC);
_EQ008 = !_LC4_A12 & _LC7_A12
# _LC7_A12 & !_LC8_A12
# _LC3_A7 & _LC4_A12 & !_LC7_A12 & _LC8_A12
# !_LC3_A7 & _LC7_A12;
-- Node name is '|DAY1:5|LPM_ADD_SUB:144|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A12', type is buried
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