📄 shuzizhong.rpt
字号:
- 6 - E 09 OR2 s 1 3 0 1 |FENLU:26|~868~1
- 5 - E 07 OR2 s 1 3 0 1 |FENLU:26|~874~1
- 7 - E 31 OR2 s 1 3 0 1 |FENLU:26|~880~1
- 1 - E 31 OR2 s 1 3 0 1 |FENLU:26|~886~1
- 2 - E 31 OR2 s 1 3 0 1 |FENLU:26|~892~1
- 1 - E 09 OR2 s 1 3 0 1 |FENLU:26|~898~1
- 7 - E 36 OR2 s 1 3 0 1 |FENLU:26|~904~1
- 7 - E 06 OR2 s 1 3 0 1 |FENLU:26|~910~1
- 3 - E 06 OR2 s 1 3 0 1 |FENLU:26|~916~1
- 7 - E 11 OR2 s 1 3 0 1 |FENLU:26|~922~1
- 7 - E 02 OR2 s 1 3 0 1 |FENLU:26|~928~1
- 5 - E 02 OR2 s 1 3 0 1 |FENLU:26|~934~1
- 1 - E 06 OR2 s 1 3 0 1 |FENLU:26|~940~1
- 7 - E 05 OR2 s 1 3 0 1 |FENLU:26|~946~1
- 4 - E 02 OR2 s 1 3 0 1 |FENLU:26|~952~1
- 7 - E 01 OR2 s 1 3 0 1 |FENLU:26|~958~1
- 6 - E 04 OR2 s 1 3 0 1 |FENLU:26|~964~1
- 2 - E 21 OR2 s 1 3 0 1 |FENLU:26|~970~1
- 8 - E 13 OR2 s 1 3 0 1 |FENLU:26|~976~1
- 8 - E 16 OR2 s 1 3 0 1 |FENLU:26|~982~1
- 2 - E 09 OR2 s 1 3 0 1 |FENLU:26|~988~1
- 6 - E 16 OR2 s 1 3 0 1 |FENLU:26|~994~1
- 8 - E 10 OR2 s 1 3 0 1 |FENLU:26|~1000~1
- 2 - E 04 OR2 s 3 0 0 24 |FENLU:26|~1000~2
- 8 - E 26 SOFT s ! 1 0 0 5 RESET~1
- 3 - E 04 AND2 s 2 0 0 24 RESET~2
- 7 - E 10 AND2 s 2 1 0 1 RESET~3
- 5 - E 10 AND2 s 2 1 0 1 RESET~4
- 3 - E 09 AND2 s 2 1 0 1 RESET~5
- 6 - E 10 AND2 s 2 1 0 1 RESET~6
- 5 - E 13 AND2 s 2 1 0 1 RESET~7
- 1 - E 21 AND2 s 2 1 0 1 RESET~8
- 4 - E 04 AND2 s 2 1 0 1 RESET~9
- 8 - E 09 AND2 s 2 1 0 1 RESET~10
- 1 - E 02 AND2 s 2 1 0 1 RESET~11
- 6 - E 05 AND2 s 2 1 0 1 RESET~12
- 4 - E 10 AND2 s 2 1 0 1 RESET~13
- 3 - E 02 AND2 s 2 1 0 1 RESET~14
- 6 - E 02 AND2 s 2 1 0 1 RESET~15
- 6 - E 11 AND2 s 2 1 0 1 RESET~16
- 2 - E 06 AND2 s 2 1 0 1 RESET~17
- 6 - E 06 AND2 s 2 1 0 1 RESET~18
- 3 - E 36 AND2 s 2 1 0 1 RESET~19
- 4 - E 09 AND2 s 2 1 0 1 RESET~20
- 4 - E 31 AND2 s 2 1 0 1 RESET~21
- 5 - E 31 AND2 s 2 1 0 1 RESET~22
- 6 - E 31 AND2 s 2 1 0 1 RESET~23
- 1 - E 07 AND2 s 2 1 0 1 RESET~24
- 5 - E 09 AND2 s 2 1 0 1 RESET~25
- 2 - E 07 AND2 s 2 1 0 1 RESET~26
- 5 - E 35 AND2 0 3 0 2 |riqi:1|DAY1:5|LPM_ADD_SUB:144|addcore:adder|:55
- 5 - E 26 DFFE 0 3 0 9 |riqi:1|DAY1:5|:20
- 8 - E 35 DFFE 1 4 0 2 |riqi:1|DAY1:5|cq13 (|riqi:1|DAY1:5|:24)
- 7 - E 35 DFFE 1 3 0 3 |riqi:1|DAY1:5|cq12 (|riqi:1|DAY1:5|:25)
- 1 - E 35 DFFE 1 4 0 3 |riqi:1|DAY1:5|cq11 (|riqi:1|DAY1:5|:26)
- 3 - E 35 DFFE 1 3 0 4 |riqi:1|DAY1:5|cq10 (|riqi:1|DAY1:5|:27)
- 1 - E 26 DFFE 1 4 0 3 |riqi:1|DAY1:5|cq03 (|riqi:1|DAY1:5|:28)
- 3 - E 26 DFFE 1 3 0 4 |riqi:1|DAY1:5|cq02 (|riqi:1|DAY1:5|:29)
- 6 - E 26 DFFE 1 4 0 5 |riqi:1|DAY1:5|cq01 (|riqi:1|DAY1:5|:30)
- 2 - E 26 DFFE ! 1 3 0 6 |riqi:1|DAY1:5|cq00 (|riqi:1|DAY1:5|:31)
- 4 - E 35 AND2 s ! 0 3 0 1 |riqi:1|DAY1:5|~69~1
- 6 - E 35 AND2 0 4 0 6 |riqi:1|DAY1:5|:69
- 8 - E 31 AND2 s 0 3 0 1 |riqi:1|DAY1:5|~135~1
- 7 - E 26 AND2 0 4 0 6 |riqi:1|DAY1:5|:135
- 4 - E 11 AND2 0 2 0 1 |riqi:1|MONTH1:2|LPM_ADD_SUB:156|addcore:adder|:55
- 7 - E 14 DFFE 0 4 0 8 |riqi:1|MONTH1:2|:20
- 5 - E 11 DFFE 1 4 0 2 |riqi:1|MONTH1:2|cq13 (|riqi:1|MONTH1:2|:24)
- 3 - E 11 DFFE 1 4 0 3 |riqi:1|MONTH1:2|cq12 (|riqi:1|MONTH1:2|:25)
- 2 - E 11 DFFE 1 3 0 4 |riqi:1|MONTH1:2|cq11 (|riqi:1|MONTH1:2|:26)
- 8 - E 14 DFFE 1 4 0 5 |riqi:1|MONTH1:2|cq10 (|riqi:1|MONTH1:2|:27)
- 3 - E 14 DFFE 1 4 0 3 |riqi:1|MONTH1:2|cq03 (|riqi:1|MONTH1:2|:28)
- 6 - E 14 DFFE 1 4 0 4 |riqi:1|MONTH1:2|cq02 (|riqi:1|MONTH1:2|:29)
- 1 - E 14 DFFE 1 4 0 6 |riqi:1|MONTH1:2|cq01 (|riqi:1|MONTH1:2|:30)
- 5 - E 14 DFFE ! 1 2 0 6 |riqi:1|MONTH1:2|cq00 (|riqi:1|MONTH1:2|:31)
- 4 - E 14 AND2 s ! 0 4 0 1 |riqi:1|MONTH1:2|~65~1
- 1 - E 11 AND2 s ! 0 4 0 3 |riqi:1|MONTH1:2|~65~2
- 2 - E 14 OR2 ! 0 4 0 7 |riqi:1|MONTH1:2|:130
- 7 - E 19 DFFE 1 4 0 2 |riqi:1|WEEK1:25|cq13 (|riqi:1|WEEK1:25|:14)
- 2 - E 19 DFFE 1 3 0 3 |riqi:1|WEEK1:25|cq12 (|riqi:1|WEEK1:25|:15)
- 1 - E 19 DFFE 1 2 0 4 |riqi:1|WEEK1:25|cq11 (|riqi:1|WEEK1:25|:16)
- 5 - E 19 DFFE 1 4 0 4 |riqi:1|WEEK1:25|cq10 (|riqi:1|WEEK1:25|:17)
- 2 - E 01 AND2 0 2 0 1 |riqi:1|YEAR1:4|LPM_ADD_SUB:59|addcore:adder|:55
- 5 - E 01 OR2 0 4 0 1 |riqi:1|YEAR1:4|LPM_ADD_SUB:59|addcore:adder|:69
- 6 - E 01 DFFE 1 4 0 3 |riqi:1|YEAR1:4|cq13 (|riqi:1|YEAR1:4|:22)
- 3 - E 01 DFFE 1 4 0 3 |riqi:1|YEAR1:4|cq12 (|riqi:1|YEAR1:4|:23)
- 4 - E 01 DFFE 1 4 0 4 |riqi:1|YEAR1:4|cq11 (|riqi:1|YEAR1:4|:24)
- 8 - E 01 DFFE 1 2 0 5 |riqi:1|YEAR1:4|cq10 (|riqi:1|YEAR1:4|:25)
- 5 - E 16 DFFE 1 4 0 2 |riqi:1|YEAR1:4|cq03 (|riqi:1|YEAR1:4|:26)
- 3 - E 16 DFFE 1 4 0 3 |riqi:1|YEAR1:4|cq02 (|riqi:1|YEAR1:4|:27)
- 2 - E 16 DFFE 1 3 0 4 |riqi:1|YEAR1:4|cq01 (|riqi:1|YEAR1:4|:28)
- 7 - E 16 DFFE 1 1 0 5 |riqi:1|YEAR1:4|cq00 (|riqi:1|YEAR1:4|:29)
- 1 - E 16 OR2 ! 0 4 0 6 |riqi:1|YEAR1:4|:45
- 1 - E 01 OR2 ! 0 4 0 3 |riqi:1|YEAR1:4|:60
- 3 - E 13 AND2 0 2 0 1 |shijian:2|HOUR1:22|LPM_ADD_SUB:144|addcore:adder|:55
- 4 - E 26 DFFE 0 3 0 13 |shijian:2|HOUR1:22|:20
- 6 - E 13 DFFE 1 4 0 2 |shijian:2|HOUR1:22|cq13 (|shijian:2|HOUR1:22|:24)
- 7 - E 13 DFFE 1 4 0 3 |shijian:2|HOUR1:22|cq12 (|shijian:2|HOUR1:22|:25)
- 4 - E 13 DFFE 1 4 0 4 |shijian:2|HOUR1:22|cq11 (|shijian:2|HOUR1:22|:26)
- 2 - E 13 DFFE 1 2 0 5 |shijian:2|HOUR1:22|cq10 (|shijian:2|HOUR1:22|:27)
- 3 - E 08 DFFE 1 4 0 3 |shijian:2|HOUR1:22|cq03 (|shijian:2|HOUR1:22|:28)
- 7 - E 08 DFFE 1 4 0 4 |shijian:2|HOUR1:22|cq02 (|shijian:2|HOUR1:22|:29)
- 4 - E 08 DFFE 1 3 0 5 |shijian:2|HOUR1:22|cq01 (|shijian:2|HOUR1:22|:30)
- 6 - E 08 DFFE 1 1 0 6 |shijian:2|HOUR1:22|cq00 (|shijian:2|HOUR1:22|:31)
- 1 - E 10 AND2 s 0 3 0 1 |shijian:2|HOUR1:22|~69~1
- 1 - E 08 AND2 s 0 3 0 1 |shijian:2|HOUR1:22|~69~2
- 3 - E 10 AND2 0 4 0 3 |shijian:2|HOUR1:22|:69
- 5 - E 08 OR2 ! 0 4 0 5 |shijian:2|HOUR1:22|:135
- 7 - E 12 AND2 0 2 0 1 |shijian:2|MINUTE1:2|LPM_ADD_SUB:63|addcore:adder|:55
- 8 - E 12 OR2 0 4 0 1 |shijian:2|MINUTE1:2|LPM_ADD_SUB:63|addcore:adder|:69
- 2 - E 12 DFFE 0 4 0 9 |shijian:2|MINUTE1:2|:20
- 1 - E 12 DFFE 1 4 0 3 |shijian:2|MINUTE1:2|cq13 (|shijian:2|MINUTE1:2|:24)
- 4 - E 12 DFFE 1 4 0 3 |shijian:2|MINUTE1:2|cq12 (|shijian:2|MINUTE1:2|:25)
- 5 - E 12 DFFE 1 4 0 4 |shijian:2|MINUTE1:2|cq11 (|shijian:2|MINUTE1:2|:26)
- 3 - E 12 DFFE 1 2 0 5 |shijian:2|MINUTE1:2|cq10 (|shijian:2|MINUTE1:2|:27)
- 2 - E 05 DFFE 1 4 0 2 |shijian:2|MINUTE1:2|cq03 (|shijian:2|MINUTE1:2|:28)
- 3 - E 05 DFFE 1 4 0 3 |shijian:2|MINUTE1:2|cq02 (|shijian:2|MINUTE1:2|:29)
- 5 - E 05 DFFE 1 3 0 4 |shijian:2|MINUTE1:2|cq01 (|shijian:2|MINUTE1:2|:30)
- 1 - E 05 DFFE 1 1 0 5 |shijian:2|MINUTE1:2|cq00 (|shijian:2|MINUTE1:2|:31)
- 4 - E 05 OR2 ! 0 4 0 7 |shijian:2|MINUTE1:2|:49
- 6 - E 12 AND2 0 4 0 4 |shijian:2|MINUTE1:2|:64
- 5 - E 15 AND2 0 2 0 1 |shijian:2|SECOND1:1|LPM_ADD_SUB:63|addcore:adder|:55
- 6 - E 15 OR2 0 4 0 1 |shijian:2|SECOND1:1|LPM_ADD_SUB:63|addcore:adder|:69
- 8 - E 15 DFFE + 0 3 0 9 |shijian:2|SECOND1:1|:20
- 1 - E 15 DFFE + 1 3 0 3 |shijian:2|SECOND1:1|cq13 (|shijian:2|SECOND1:1|:24)
- 2 - E 15 DFFE + 1 3 0 3 |shijian:2|SECOND1:1|cq12 (|shijian:2|SECOND1:1|:25)
- 3 - E 15 DFFE + 1 3 0 4 |shijian:2|SECOND1:1|cq11 (|shijian:2|SECOND1:1|:26)
- 7 - E 15 DFFE + 1 1 0 5 |shijian:2|SECOND1:1|cq10 (|shijian:2|SECOND1:1|:27)
- 2 - E 36 DFFE + 1 3 0 2 |shijian:2|SECOND1:1|cq03 (|shijian:2|SECOND1:1|:28)
- 4 - E 36 DFFE + 1 3 0 3 |shijian:2|SECOND1:1|cq02 (|shijian:2|SECOND1:1|:29)
- 8 - E 36 DFFE + 1 2 0 4 |shijian:2|SECOND1:1|cq01 (|shijian:2|SECOND1:1|:30)
- 1 - E 36 DFFE + 1 0 0 5 |shijian:2|SECOND1:1|cq00 (|shijian:2|SECOND1:1|:31)
- 5 - E 36 OR2 ! 0 4 0 7 |shijian:2|SECOND1:1|:49
- 4 - E 15 AND2 0 4 0 4 |shijian:2|SECOND1:1|:64
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\clock\shuzizhong.rpt
shuzizhong
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 3/144( 2%) 0/ 72( 0%) 0/ 72( 0%) 3/16( 18%) 0/16( 0%) 0/16( 0%)
D: 2/144( 1%) 2/ 72( 2%) 0/ 72( 0%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
E: 79/144( 54%) 6/ 72( 8%) 3/ 72( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
F: 1/144( 0%) 5/ 72( 6%) 3/ 72( 4%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
32: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
34: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
35: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
36: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\clock\shuzizhong.rpt
shuzizhong
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 37 CLK
DFF 13 |shijian:2|HOUR1:22|:20
DFF 10 |shijian:2|MINUTE1:2|:20
DFF 10 |shijian:2|SECOND1:1|:20
DFF 9 |riqi:1|DAY1:5|:20
DFF 8 |riqi:1|MONTH1:2|:20
Device-Specific Information: c:\clock\shuzizhong.rpt
shuzizhong
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 81 RESET
Device-Specific Information: c:\clock\shuzizhong.rpt
shuzizhong
** EQUATIONS **
CLK : INPUT;
EN0 : INPUT;
EN1 : INPUT;
RESET : INPUT;
SET : INPUT;
-- Node name is 'D00'
-- Equation name is 'D00', type is output
D00 = _LC1_E4;
-- Node name is 'D01'
-- Equation name is 'D01', type is output
D01 = _LC3_E19;
-- Node name is 'D02'
-- Equation name is 'D02', type is output
D02 = _LC5_E21;
-- Node name is 'D03'
-- Equation name is 'D03', type is output
D03 = _LC7_E21;
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