📄 shuzizhong.rpt
字号:
EN1 | 17 92 | RESERVED
SET | 18 91 | RESERVED
RESET | 19 EP1K30TC144-3 90 | D53
RESERVED | 20 89 | D52
RESERVED | 21 88 | D51
RESERVED | 22 87 | D50
RESERVED | 23 86 | D63
VCCIO | 24 85 | VCCINT
GND | 25 84 | GND
RESERVED | 26 83 | D62
RESERVED | 27 82 | D61
RESERVED | 28 81 | D60
RESERVED | 29 80 | D33
D00 | 30 79 | D32
D01 | 31 78 | D31
D02 | 32 77 | ^MSEL0
D03 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
D20 | 36 73 | D30
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
D D D G D D R R V R R R R V R G V G G G G G R R V R R R D G D D D D V D
2 2 2 N 1 1 E E C E E E E C E N C N N N N N E E C E E E 1 N 1 4 4 4 C 4
1 2 3 D 0 1 S S C S S S S C S D C D D D D D S S C S S S 2 D 3 0 1 2 C 3
E E I E E E E I E I E E I E E E I
R R O R R R R N R N R R O R R R O
V V V V V V T V T V V V V V
E E E E E E E E E E E E
D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: c:\clock\shuzizhong.rpt
shuzizhong
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
E1 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 6/22( 27%)
E2 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 13/22( 59%)
E3 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 4/22( 18%)
E4 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
E5 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 8/22( 36%)
E6 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 12/22( 54%)
E7 5/ 8( 62%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 10/22( 45%)
E8 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 2/2 1/2 6/22( 27%)
E9 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 13/22( 59%)
E10 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 16/22( 72%)
E11 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 11/22( 50%)
E12 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 4/22( 18%)
E13 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 10/22( 45%)
E14 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 1/2 4/22( 18%)
E15 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
E16 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 7/22( 31%)
E19 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 6/22( 27%)
E21 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 10/22( 45%)
E26 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 2/2 1/2 4/22( 18%)
E27 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 3/22( 13%)
E31 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 14/22( 63%)
E33 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 4/22( 18%)
E35 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 2/2 1/2 7/22( 31%)
E36 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 32/96 ( 33%)
Total logic cells used: 170/1728 ( 9%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.50/4 ( 87%)
Total fan-in: 596/6912 ( 8%)
Total input pins required: 5
Total input I/O cell registers required: 0
Total output pins required: 28
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 170
Total flipflops required: 85
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 57/1728 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 8 8 2 8 8 8 5 8 8 8 8 8 8 8 8 8 0 0 0 8 0 8 0 0 0 0 8 1 0 0 0 8 0 2 0 8 8 170/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 8 2 8 8 8 5 8 8 8 8 8 8 8 8 8 0 0 0 8 0 8 0 0 0 0 8 1 0 0 0 8 0 2 0 8 8 170/0
Device-Specific Information: c:\clock\shuzizhong.rpt
shuzizhong
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
126 - - - -- INPUT G ^ 0 0 0 0 CLK
13 - - C -- INPUT ^ 0 0 0 34 EN0
17 - - C -- INPUT ^ 0 0 0 34 EN1
19 - - D -- INPUT ^ 0 0 0 81 RESET
18 - - C -- INPUT ^ 0 0 0 33 SET
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\clock\shuzizhong.rpt
shuzizhong
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
30 - - F -- OUTPUT 0 1 0 0 D00
31 - - F -- OUTPUT 0 1 0 0 D01
32 - - F -- OUTPUT 0 1 0 0 D02
33 - - F -- OUTPUT 0 1 0 0 D03
41 - - - 31 OUTPUT 0 1 0 0 D10
42 - - - 28 OUTPUT 0 1 0 0 D11
65 - - - 09 OUTPUT 0 1 0 0 D12
67 - - - 08 OUTPUT 0 1 0 0 D13
36 - - - 36 OUTPUT 0 1 0 0 D20
37 - - - 35 OUTPUT 0 1 0 0 D21
38 - - - 34 OUTPUT 0 1 0 0 D22
39 - - - 33 OUTPUT 0 1 0 0 D23
73 - - - 01 OUTPUT 0 1 0 0 D30
78 - - F -- OUTPUT 0 1 0 0 D31
79 - - F -- OUTPUT 0 1 0 0 D32
80 - - F -- OUTPUT 0 1 0 0 D33
68 - - - 07 OUTPUT 0 1 0 0 D40
69 - - - 06 OUTPUT 0 1 0 0 D41
70 - - - 05 OUTPUT 0 1 0 0 D42
72 - - - 03 OUTPUT 0 1 0 0 D43
87 - - E -- OUTPUT 0 1 0 0 D50
88 - - D -- OUTPUT 0 1 0 0 D51
89 - - D -- OUTPUT 0 1 0 0 D52
90 - - D -- OUTPUT 0 1 0 0 D53
81 - - F -- OUTPUT 0 1 0 0 D60
82 - - F -- OUTPUT 0 1 0 0 D61
83 - - E -- OUTPUT 0 1 0 0 D62
86 - - E -- OUTPUT 0 1 0 0 D63
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\clock\shuzizhong.rpt
shuzizhong
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - E 21 DFFE + 2 1 1 1 |FENLU:26|Q03 (|FENLU:26|:90)
- 5 - E 21 DFFE + 2 1 1 1 |FENLU:26|Q02 (|FENLU:26|:91)
- 3 - E 19 DFFE + 2 1 1 1 |FENLU:26|Q01 (|FENLU:26|:92)
- 1 - E 04 DFFE + 2 1 1 1 |FENLU:26|Q00 (|FENLU:26|:93)
- 3 - E 07 DFFE + 1 2 1 0 |FENLU:26|Q13 (|FENLU:26|:94)
- 7 - E 09 DFFE + 1 2 1 0 |FENLU:26|Q12 (|FENLU:26|:95)
- 4 - E 27 DFFE + 1 2 1 0 |FENLU:26|Q11 (|FENLU:26|:96)
- 3 - E 31 DFFE + 1 2 1 0 |FENLU:26|Q10 (|FENLU:26|:97)
- 2 - E 33 DFFE + 1 2 1 0 |FENLU:26|Q23 (|FENLU:26|:98)
- 1 - E 33 DFFE + 1 2 1 0 |FENLU:26|Q22 (|FENLU:26|:99)
- 2 - E 35 DFFE + 1 2 1 0 |FENLU:26|Q21 (|FENLU:26|:100)
- 6 - E 36 DFFE + 1 2 1 0 |FENLU:26|Q20 (|FENLU:26|:101)
- 4 - E 06 DFFE + 1 2 1 0 |FENLU:26|Q33 (|FENLU:26|:102)
- 5 - E 06 DFFE + 1 2 1 0 |FENLU:26|Q32 (|FENLU:26|:103)
- 8 - E 11 DFFE + 1 2 1 0 |FENLU:26|Q31 (|FENLU:26|:104)
- 2 - E 02 DFFE + 1 2 1 0 |FENLU:26|Q30 (|FENLU:26|:105)
- 8 - E 03 DFFE + 1 2 1 0 |FENLU:26|Q43 (|FENLU:26|:106)
- 8 - E 06 DFFE + 1 2 1 0 |FENLU:26|Q42 (|FENLU:26|:107)
- 8 - E 05 DFFE + 1 2 1 0 |FENLU:26|Q41 (|FENLU:26|:108)
- 2 - E 08 DFFE + 1 2 1 0 |FENLU:26|Q40 (|FENLU:26|:109)
- 8 - E 02 DFFE + 1 2 1 0 |FENLU:26|Q53 (|FENLU:26|:110)
- 5 - E 04 DFFE + 1 2 1 0 |FENLU:26|Q52 (|FENLU:26|:111)
- 8 - E 21 DFFE + 1 2 1 0 |FENLU:26|Q51 (|FENLU:26|:112)
- 1 - E 13 DFFE + 1 2 1 0 |FENLU:26|Q50 (|FENLU:26|:113)
- 4 - E 16 DFFE + 1 2 1 0 |FENLU:26|Q63 (|FENLU:26|:114)
- 8 - E 08 DFFE + 1 2 1 0 |FENLU:26|Q62 (|FENLU:26|:115)
- 1 - E 03 DFFE + 1 2 1 0 |FENLU:26|Q61 (|FENLU:26|:116)
- 2 - E 10 DFFE + 1 2 1 0 |FENLU:26|Q60 (|FENLU:26|:117)
- 4 - E 21 OR2 2 2 0 1 |FENLU:26|:345
- 8 - E 19 OR2 2 2 0 1 |FENLU:26|:357
- 4 - E 19 OR2 2 2 0 1 |FENLU:26|:366
- 7 - E 04 OR2 2 2 0 1 |FENLU:26|:375
- 6 - E 21 OR2 3 1 0 1 |FENLU:26|:663
- 3 - E 21 OR2 3 1 0 1 |FENLU:26|:669
- 6 - E 19 OR2 3 1 0 1 |FENLU:26|:675
- 8 - E 04 OR2 3 1 0 1 |FENLU:26|:681
- 4 - E 07 OR2 s 1 3 0 1 |FENLU:26|~862~1
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -