shuzizhong.rpt

能自动记时

Project Information                                    c:\clock\shuzizhong.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 06/30/2007 08:27:31

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

shuzizhong
      EP1K30TC144-3        5      28     0    0         0  %    170      9  %

User Pins:                 5      28     0  



Project Information                                    c:\clock\shuzizhong.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Ignored unnecessary INPUT pin 'A03'
Warning: Ignored unnecessary INPUT pin 'A02'
Warning: Ignored unnecessary INPUT pin 'A01'
Warning: Ignored unnecessary INPUT pin 'A00'
Warning: Ignored unnecessary INPUT pin 'A13'
Warning: Ignored unnecessary INPUT pin 'A12'
Warning: Ignored unnecessary INPUT pin 'A11'
Warning: Ignored unnecessary INPUT pin 'A10'
Warning: Ignored unnecessary INPUT pin 'A23'
Warning: Ignored unnecessary INPUT pin 'A22'
Warning: Ignored unnecessary INPUT pin 'A21'
Warning: Ignored unnecessary INPUT pin 'A20'
Warning: Ignored unnecessary INPUT pin 'A33'
Warning: Ignored unnecessary INPUT pin 'A32'
Warning: Ignored unnecessary INPUT pin 'A31'
Warning: Ignored unnecessary INPUT pin 'A30'
Warning: Ignored unnecessary INPUT pin 'A43'
Warning: Ignored unnecessary INPUT pin 'A42'
Warning: Ignored unnecessary INPUT pin 'A41'
Warning: Ignored unnecessary INPUT pin 'A40'
Warning: Ignored unnecessary INPUT pin 'A53'
Warning: Ignored unnecessary INPUT pin 'A52'
Warning: Ignored unnecessary INPUT pin 'A51'
Warning: Ignored unnecessary INPUT pin 'A50'
Warning: Ignored unnecessary INPUT pin 'A63'
Warning: Ignored unnecessary INPUT pin 'A62'
Warning: Ignored unnecessary INPUT pin 'A61'
Warning: Ignored unnecessary INPUT pin 'A60'


Project Information                                    c:\clock\shuzizhong.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

shuzizhong@126                    CLK
shuzizhong@30                     D00
shuzizhong@31                     D01
shuzizhong@32                     D02
shuzizhong@33                     D03
shuzizhong@41                     D10
shuzizhong@42                     D11
shuzizhong@65                     D12
shuzizhong@67                     D13
shuzizhong@36                     D20
shuzizhong@37                     D21
shuzizhong@38                     D22
shuzizhong@39                     D23
shuzizhong@73                     D30
shuzizhong@78                     D31
shuzizhong@79                     D32
shuzizhong@80                     D33
shuzizhong@68                     D40
shuzizhong@69                     D41
shuzizhong@70                     D42
shuzizhong@72                     D43
shuzizhong@87                     D50
shuzizhong@88                     D51
shuzizhong@89                     D52
shuzizhong@90                     D53
shuzizhong@81                     D60
shuzizhong@82                     D61
shuzizhong@83                     D62
shuzizhong@86                     D63
shuzizhong@13                     EN0
shuzizhong@17                     EN1
shuzizhong@19                     RESET
shuzizhong@18                     SET


Project Information                                    c:\clock\shuzizhong.rpt

** FILE HIERARCHY **



|riqi:1|
|riqi:1|month1:2|
|riqi:1|month1:2|lpm_add_sub:151|
|riqi:1|month1:2|lpm_add_sub:151|addcore:adder|
|riqi:1|month1:2|lpm_add_sub:151|altshift:result_ext_latency_ffs|
|riqi:1|month1:2|lpm_add_sub:151|altshift:carry_ext_latency_ffs|
|riqi:1|month1:2|lpm_add_sub:151|altshift:oflow_ext_latency_ffs|
|riqi:1|month1:2|lpm_add_sub:156|
|riqi:1|month1:2|lpm_add_sub:156|addcore:adder|
|riqi:1|month1:2|lpm_add_sub:156|altshift:result_ext_latency_ffs|
|riqi:1|month1:2|lpm_add_sub:156|altshift:carry_ext_latency_ffs|
|riqi:1|month1:2|lpm_add_sub:156|altshift:oflow_ext_latency_ffs|
|riqi:1|year1:4|
|riqi:1|year1:4|lpm_add_sub:44|
|riqi:1|year1:4|lpm_add_sub:44|addcore:adder|
|riqi:1|year1:4|lpm_add_sub:44|altshift:result_ext_latency_ffs|
|riqi:1|year1:4|lpm_add_sub:44|altshift:carry_ext_latency_ffs|
|riqi:1|year1:4|lpm_add_sub:44|altshift:oflow_ext_latency_ffs|
|riqi:1|year1:4|lpm_add_sub:59|
|riqi:1|year1:4|lpm_add_sub:59|addcore:adder|
|riqi:1|year1:4|lpm_add_sub:59|altshift:result_ext_latency_ffs|
|riqi:1|year1:4|lpm_add_sub:59|altshift:carry_ext_latency_ffs|
|riqi:1|year1:4|lpm_add_sub:59|altshift:oflow_ext_latency_ffs|
|riqi:1|day1:5|
|riqi:1|day1:5|lpm_add_sub:134|
|riqi:1|day1:5|lpm_add_sub:134|addcore:adder|
|riqi:1|day1:5|lpm_add_sub:134|altshift:result_ext_latency_ffs|
|riqi:1|day1:5|lpm_add_sub:134|altshift:carry_ext_latency_ffs|
|riqi:1|day1:5|lpm_add_sub:134|altshift:oflow_ext_latency_ffs|
|riqi:1|day1:5|lpm_add_sub:144|
|riqi:1|day1:5|lpm_add_sub:144|addcore:adder|
|riqi:1|day1:5|lpm_add_sub:144|altshift:result_ext_latency_ffs|
|riqi:1|day1:5|lpm_add_sub:144|altshift:carry_ext_latency_ffs|
|riqi:1|day1:5|lpm_add_sub:144|altshift:oflow_ext_latency_ffs|
|riqi:1|week1:25|
|riqi:1|week1:25|lpm_add_sub:28|
|riqi:1|week1:25|lpm_add_sub:28|addcore:adder|
|riqi:1|week1:25|lpm_add_sub:28|altshift:result_ext_latency_ffs|
|riqi:1|week1:25|lpm_add_sub:28|altshift:carry_ext_latency_ffs|
|riqi:1|week1:25|lpm_add_sub:28|altshift:oflow_ext_latency_ffs|
|shijian:2|
|shijian:2|second1:1|
|shijian:2|second1:1|lpm_add_sub:48|
|shijian:2|second1:1|lpm_add_sub:48|addcore:adder|
|shijian:2|second1:1|lpm_add_sub:48|altshift:result_ext_latency_ffs|
|shijian:2|second1:1|lpm_add_sub:48|altshift:carry_ext_latency_ffs|
|shijian:2|second1:1|lpm_add_sub:48|altshift:oflow_ext_latency_ffs|
|shijian:2|second1:1|lpm_add_sub:63|
|shijian:2|second1:1|lpm_add_sub:63|addcore:adder|
|shijian:2|second1:1|lpm_add_sub:63|altshift:result_ext_latency_ffs|
|shijian:2|second1:1|lpm_add_sub:63|altshift:carry_ext_latency_ffs|
|shijian:2|second1:1|lpm_add_sub:63|altshift:oflow_ext_latency_ffs|
|shijian:2|minute1:2|
|shijian:2|minute1:2|lpm_add_sub:48|
|shijian:2|minute1:2|lpm_add_sub:48|addcore:adder|
|shijian:2|minute1:2|lpm_add_sub:48|altshift:result_ext_latency_ffs|
|shijian:2|minute1:2|lpm_add_sub:48|altshift:carry_ext_latency_ffs|
|shijian:2|minute1:2|lpm_add_sub:48|altshift:oflow_ext_latency_ffs|
|shijian:2|minute1:2|lpm_add_sub:63|
|shijian:2|minute1:2|lpm_add_sub:63|addcore:adder|
|shijian:2|minute1:2|lpm_add_sub:63|altshift:result_ext_latency_ffs|
|shijian:2|minute1:2|lpm_add_sub:63|altshift:carry_ext_latency_ffs|
|shijian:2|minute1:2|lpm_add_sub:63|altshift:oflow_ext_latency_ffs|
|shijian:2|hour1:22|
|shijian:2|hour1:22|lpm_add_sub:134|
|shijian:2|hour1:22|lpm_add_sub:134|addcore:adder|
|shijian:2|hour1:22|lpm_add_sub:134|altshift:result_ext_latency_ffs|
|shijian:2|hour1:22|lpm_add_sub:134|altshift:carry_ext_latency_ffs|
|shijian:2|hour1:22|lpm_add_sub:134|altshift:oflow_ext_latency_ffs|
|shijian:2|hour1:22|lpm_add_sub:144|
|shijian:2|hour1:22|lpm_add_sub:144|addcore:adder|
|shijian:2|hour1:22|lpm_add_sub:144|altshift:result_ext_latency_ffs|
|shijian:2|hour1:22|lpm_add_sub:144|altshift:carry_ext_latency_ffs|
|shijian:2|hour1:22|lpm_add_sub:144|altshift:oflow_ext_latency_ffs|
|xuanze:4|
|fenlu:26|


Device-Specific Information:                           c:\clock\shuzizhong.rpt
shuzizhong

***** Logic for device 'shuzizhong' compiled without errors.




Device: EP1K30TC144-3

ACEX 1K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f
    MultiVolt I/O                              = OFF

                                                                                         
                                                                                         
                R R R R R   R R R R   R R R R   R           R R R R R R R   R R R R R R  
                E E E E E   E E E E   E E E E   E           E E E E E E E   E E E E E E  
                S S S S S   S S S S   S S S S   S V         S S S S S S S   S S S S S S  
                E E E E E   E E E E V E E E E   E C         E E E E E E E V E E E E E E  
                R R R R R   R R R R C R R R R   R C         R R R R R R R C R R R R R R  
                V V V V V G V V V V C V V V V G V I C G G G V V V V V V V C V V V V V V  
                E E E E E N E E E E I E E E E N E N L N N N E E E E E E E I E E E E E E  
                D D D D D D D D D D O D D D D D D T K D D D D D D D D D D O D D D D D D  
              --------------------------------------------------------------------------_ 
             / 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110   |_ 
            /    143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109    | 
      #TCK |  1                                                                         108 | ^DATA0 
^CONF_DONE |  2                                                                         107 | ^DCLK 
     ^nCEO |  3                                                                         106 | ^nCE 
      #TDO |  4                                                                         105 | #TDI 
     VCCIO |  5                                                                         104 | GND 
       GND |  6                                                                         103 | VCCINT 
  RESERVED |  7                                                                         102 | RESERVED 
  RESERVED |  8                                                                         101 | RESERVED 
  RESERVED |  9                                                                         100 | RESERVED 
  RESERVED | 10                                                                          99 | RESERVED 
  RESERVED | 11                                                                          98 | RESERVED 
  RESERVED | 12                                                                          97 | RESERVED 
       EN0 | 13                                                                          96 | RESERVED 
  RESERVED | 14                                                                          95 | RESERVED 
       GND | 15                                                                          94 | VCCIO 
    VCCINT | 16                                                                          93 | GND