📄 fenlu.pin
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-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
----------------------------------------------------------------------------
CHIP "fenlu" ASSIGNED TO AN EP1K10TC144-1
TCK : 1
CONF_DONE : 2
nCEO : 3
TDO : 4
VCCIO : 5
N.C. : 6
d63 : 7
b02 : 8
d50 : 9
N.C. : 10
d10 : 11
N.C. : 12
c53 : 13
d31 : 14
GND : 15
VCCINT : 16
b60 : 17
c20 : 18
c51 : 19
N.C. : 20
b43 : 21
N.C. : 22
b20 : 23
VCCIO : 24
GND : 25
d01 : 26
d41 : 27
N.C. : 28
c32 : 29
c01 : 30
N.C. : 31
c41 : 32
d42 : 33
TMS : 34
nSTATUS : 35
b30 : 36
b40 : 37
b10 : 38
d53 : 39
GND : 40
b52 : 41
c63 : 42
c30 : 43
d02 : 44
VCCIO : 45
b11 : 46
d62 : 47
c11 : 48
d11 : 49
VCCINT : 50
d23 : 51
GND : 52
VCC_CKLK : 53
en0 : 54
clk : 55
en1 : 56
GND_CKLK : 57
GND : 58
c43 : 59
c03 : 60
VCCIO : 61
b22 : 62
c12 : 63
c52 : 64
d61 : 65
GND : 66
c62 : 67
b32 : 68
b21 : 69
d32 : 70
VCCIO : 71
c33 : 72
d22 : 73
nCONFIG : 74
VCCINT : 75
MSEL1 : 76
MSEL0 : 77
d33 : 78
c42 : 79
d03 : 80
b01 : 81
N.C. : 82
b03 : 83
GND : 84
VCCINT : 85
d51 : 86
d13 : 87
b13 : 88
N.C. : 89
d12 : 90
d52 : 91
d43 : 92
GND : 93
VCCIO : 94
c23 : 95
b42 : 96
b00 : 97
b62 : 98
N.C. : 99
b23 : 100
N.C. : 101
c00 : 102
VCCINT : 103
N.C. : 104
TDI : 105
nCE : 106
DCLK : 107
DATA0 : 108
c61 : 109
d21 : 110
b61 : 111
d20 : 112
c13 : 113
b12 : 114
VCCIO : 115
c22 : 116
c21 : 117
RESERVED : 118
b51 : 119
RESERVED : 120
d60 : 121
RESERVED : 122
GND : 123
set : 124
c60 : 125
reset : 126
VCCINT : 127
b50 : 128
GND : 129
c02 : 130
c31 : 131
b31 : 132
d30 : 133
VCCIO : 134
c10 : 135
b33 : 136
b63 : 137
c50 : 138
GND : 139
d00 : 140
d40 : 141
c40 : 142
b53 : 143
b41 : 144
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