📄 year1.rpt
字号:
- 1 - B 02 AND2 0 2 0 1 |LPM_ADD_SUB:64|addcore:adder|:55
- 8 - B 02 DFFE + 0 3 1 0 cq13 (:22)
- 3 - B 04 DFFE + 0 3 1 1 cq12 (:23)
- 8 - B 04 DFFE + 0 2 1 2 cq11 (:24)
- 6 - B 04 DFFE + 0 1 1 3 cq10 (:25)
- 1 - B 04 DFFE + 0 3 1 1 cq03 (:26)
- 5 - B 04 DFFE + 0 3 1 2 cq02 (:27)
- 4 - B 04 DFFE + 0 2 1 3 cq01 (:28)
- 2 - B 04 DFFE + ! 0 0 1 4 cq00 (:29)
- 7 - B 04 OR2 ! 0 4 0 6 :45
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\mp2student\clock5\year1.rpt
year1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 4/ 96( 4%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\mp2student\clock5\year1.rpt
year1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clky
Device-Specific Information: e:\mp2student\clock5\year1.rpt
year1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 reset
Device-Specific Information: e:\mp2student\clock5\year1.rpt
year1
** EQUATIONS **
clky : INPUT;
reset : INPUT;
-- Node name is ':29' = 'cq00'
-- Equation name is 'cq00', location is LC2_B4, type is buried.
!cq00 = cq00~NOT;
cq00~NOT = DFFE( cq00, GLOBAL( clky), GLOBAL(!reset), VCC, VCC);
-- Node name is ':28' = 'cq01'
-- Equation name is 'cq01', location is LC4_B4, type is buried.
cq01 = DFFE( _EQ001, GLOBAL( clky), GLOBAL(!reset), VCC, VCC);
_EQ001 = !cq00 & cq01 & !_LC7_B4
# cq00 & !cq01 & !_LC7_B4;
-- Node name is ':27' = 'cq02'
-- Equation name is 'cq02', location is LC5_B4, type is buried.
cq02 = DFFE( _EQ002, GLOBAL( clky), GLOBAL(!reset), VCC, VCC);
_EQ002 = !cq01 & cq02 & !_LC7_B4
# !cq00 & cq02 & !_LC7_B4
# cq00 & cq01 & !cq02 & !_LC7_B4;
-- Node name is ':26' = 'cq03'
-- Equation name is 'cq03', location is LC1_B4, type is buried.
cq03 = DFFE( _EQ003, GLOBAL( clky), GLOBAL(!reset), VCC, VCC);
_EQ003 = !cq00 & cq03
# cq00 & cq01 & cq02 & !cq03
# !cq01 & cq02 & cq03
# cq01 & !cq02 & cq03;
-- Node name is ':25' = 'cq10'
-- Equation name is 'cq10', location is LC6_B4, type is buried.
cq10 = DFFE( _EQ004, GLOBAL( clky), GLOBAL(!reset), VCC, VCC);
_EQ004 = cq10 & !_LC7_B4
# !cq10 & _LC7_B4;
-- Node name is ':24' = 'cq11'
-- Equation name is 'cq11', location is LC8_B4, type is buried.
cq11 = DFFE( _EQ005, GLOBAL( clky), GLOBAL(!reset), VCC, VCC);
_EQ005 = !cq10 & cq11
# cq10 & !cq11 & _LC7_B4
# cq11 & !_LC7_B4;
-- Node name is ':23' = 'cq12'
-- Equation name is 'cq12', location is LC3_B4, type is buried.
cq12 = DFFE( _EQ006, GLOBAL( clky), GLOBAL(!reset), VCC, VCC);
_EQ006 = !cq11 & cq12
# !cq10 & cq12
# cq10 & cq11 & !cq12 & _LC7_B4
# cq12 & !_LC7_B4;
-- Node name is ':22' = 'cq13'
-- Equation name is 'cq13', location is LC8_B2, type is buried.
cq13 = DFFE( _EQ007, GLOBAL( clky), GLOBAL(!reset), VCC, VCC);
_EQ007 = cq13 & !_LC1_B2
# !cq12 & cq13
# cq12 & !cq13 & _LC1_B2 & _LC7_B4
# cq13 & !_LC7_B4;
-- Node name is 'year00'
-- Equation name is 'year00', type is output
year00 = cq00;
-- Node name is 'year01'
-- Equation name is 'year01', type is output
year01 = cq01;
-- Node name is 'year02'
-- Equation name is 'year02', type is output
year02 = cq02;
-- Node name is 'year03'
-- Equation name is 'year03', type is output
year03 = cq03;
-- Node name is 'year10'
-- Equation name is 'year10', type is output
year10 = cq10;
-- Node name is 'year11'
-- Equation name is 'year11', type is output
year11 = cq11;
-- Node name is 'year12'
-- Equation name is 'year12', type is output
year12 = cq12;
-- Node name is 'year13'
-- Equation name is 'year13', type is output
year13 = cq13;
-- Node name is '|LPM_ADD_SUB:64|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ008);
_EQ008 = cq10 & cq11;
-- Node name is ':45'
-- Equation name is '_LC7_B4', type is buried
!_LC7_B4 = _LC7_B4~NOT;
_LC7_B4~NOT = LCELL( _EQ009);
_EQ009 = cq01
# !cq03
# cq02
# !cq00;
Project Information e:\mp2student\clock5\year1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:02
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,241K
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