📄 shijian.rpt
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_EQ006 = _LC1_C2 & !_LC5_C2
# _LC1_C2 & !_LC4_C2
# !_LC1_C2 & _LC1_C5 & _LC4_C2 & _LC5_C2
# _LC1_C2 & !_LC1_C5;
-- Node name is '|HOUR1:22|:24' = '|HOUR1:22|cq13'
-- Equation name is '_LC6_C2', type is buried
_LC6_C2 = DFFE( _EQ007, _LC8_C2, GLOBAL(!RESET), VCC, VCC);
_EQ007 = _LC6_C2 & !_LC7_C2
# !_LC1_C2 & _LC6_C2
# _LC1_C2 & _LC1_C5 & !_LC6_C2 & _LC7_C2
# !_LC1_C5 & _LC6_C2;
-- Node name is '|HOUR1:22|LPM_ADD_SUB:144|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C2', type is buried
_LC7_C2 = LCELL( _EQ008);
_EQ008 = _LC4_C2 & _LC5_C2;
-- Node name is '|HOUR1:22|:20'
-- Equation name is '_LC4_C5', type is buried
_LC4_C5 = DFFE( _LC6_C5, _LC8_C2, VCC, VCC, !_LC3_C2);
-- Node name is '|HOUR1:22|~69~1'
-- Equation name is '_LC2_C2', type is buried
-- synthesized logic cell
_LC2_C2 = LCELL( _EQ009);
_EQ009 = _LC1_C2
# !_LC5_C2
# _LC4_C2;
-- Node name is '|HOUR1:22|~69~2'
-- Equation name is '_LC8_C5', type is buried
-- synthesized logic cell
_LC8_C5 = LCELL( _EQ010);
_EQ010 = !_LC7_C5
# _LC5_C5
# _LC2_C5;
-- Node name is '|HOUR1:22|:69'
-- Equation name is '_LC6_C5', type is buried
!_LC6_C5 = _LC6_C5~NOT;
_LC6_C5~NOT = LCELL( _EQ011);
_EQ011 = _LC6_C2
# _LC2_C2
# _LC3_C5
# _LC8_C5;
-- Node name is '|HOUR1:22|:135'
-- Equation name is '_LC1_C5', type is buried
_LC1_C5 = LCELL( _EQ012);
_EQ012 = _LC2_C5 & _LC3_C5 & !_LC5_C5 & !_LC7_C5;
-- Node name is '|MINUTE1:2|:31' = '|MINUTE1:2|cq00'
-- Equation name is '_LC1_C3', type is buried
_LC1_C3 = DFFE(!_LC1_C3, _LC2_C12, GLOBAL(!RESET), VCC, VCC);
-- Node name is '|MINUTE1:2|:30' = '|MINUTE1:2|cq01'
-- Equation name is '_LC3_C9', type is buried
_LC3_C9 = DFFE( _EQ013, _LC2_C12, GLOBAL(!RESET), VCC, VCC);
_EQ013 = !_LC1_C3 & _LC3_C9 & !_LC5_C12
# _LC1_C3 & !_LC3_C9 & !_LC5_C12;
-- Node name is '|MINUTE1:2|:29' = '|MINUTE1:2|cq02'
-- Equation name is '_LC6_C12', type is buried
_LC6_C12 = DFFE( _EQ014, _LC2_C12, GLOBAL(!RESET), VCC, VCC);
_EQ014 = !_LC3_C9 & !_LC5_C12 & _LC6_C12
# !_LC1_C3 & !_LC5_C12 & _LC6_C12
# _LC1_C3 & _LC3_C9 & !_LC5_C12 & !_LC6_C12;
-- Node name is '|MINUTE1:2|:28' = '|MINUTE1:2|cq03'
-- Equation name is '_LC8_C12', type is buried
_LC8_C12 = DFFE( _EQ015, _LC2_C12, GLOBAL(!RESET), VCC, VCC);
_EQ015 = !_LC1_C3 & _LC8_C12
# _LC1_C3 & _LC3_C9 & _LC6_C12 & !_LC8_C12
# !_LC3_C9 & _LC6_C12 & _LC8_C12
# _LC3_C9 & !_LC6_C12 & _LC8_C12;
-- Node name is '|MINUTE1:2|:27' = '|MINUTE1:2|cq10'
-- Equation name is '_LC6_C9', type is buried
_LC6_C9 = DFFE( _EQ016, _LC2_C12, GLOBAL(!RESET), VCC, VCC);
_EQ016 = !_LC5_C12 & _LC6_C9
# _LC5_C12 & !_LC6_C9;
-- Node name is '|MINUTE1:2|:26' = '|MINUTE1:2|cq11'
-- Equation name is '_LC1_C9', type is buried
_LC1_C9 = DFFE( _EQ017, _LC2_C12, GLOBAL(!RESET), VCC, VCC);
_EQ017 = _LC1_C9 & !_LC5_C9 & !_LC6_C9
# !_LC1_C9 & !_LC5_C9 & _LC5_C12 & _LC6_C9
# _LC1_C9 & !_LC5_C12;
-- Node name is '|MINUTE1:2|:25' = '|MINUTE1:2|cq12'
-- Equation name is '_LC8_C9', type is buried
_LC8_C9 = DFFE( _EQ018, _LC2_C12, GLOBAL(!RESET), VCC, VCC);
_EQ018 = !_LC4_C9 & !_LC5_C9 & _LC8_C9
# _LC4_C9 & !_LC5_C9 & _LC5_C12 & !_LC8_C9
# !_LC5_C12 & _LC8_C9;
-- Node name is '|MINUTE1:2|:24' = '|MINUTE1:2|cq13'
-- Equation name is '_LC2_C9', type is buried
_LC2_C9 = DFFE( _EQ019, _LC2_C12, GLOBAL(!RESET), VCC, VCC);
_EQ019 = !_LC5_C9 & _LC5_C12 & _LC7_C9
# _LC2_C9 & !_LC5_C12;
-- Node name is '|MINUTE1:2|LPM_ADD_SUB:63|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C9', type is buried
_LC4_C9 = LCELL( _EQ020);
_EQ020 = _LC1_C9 & _LC6_C9;
-- Node name is '|MINUTE1:2|LPM_ADD_SUB:63|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_C9', type is buried
_LC7_C9 = LCELL( _EQ021);
_EQ021 = !_LC1_C9 & _LC2_C9
# _LC2_C9 & !_LC6_C9
# _LC2_C9 & !_LC8_C9
# _LC1_C9 & !_LC2_C9 & _LC6_C9 & _LC8_C9;
-- Node name is '|MINUTE1:2|:20'
-- Equation name is '_LC8_C2', type is buried
_LC8_C2 = DFFE( _EQ022, _LC2_C12, VCC, VCC, !_LC3_C2);
_EQ022 = _LC5_C9 & _LC5_C12
# !_LC5_C12 & _LC8_C2;
-- Node name is '|MINUTE1:2|:49'
-- Equation name is '_LC5_C12', type is buried
!_LC5_C12 = _LC5_C12~NOT;
_LC5_C12~NOT = LCELL( _EQ023);
_EQ023 = !_LC1_C3
# _LC3_C9
# !_LC8_C12
# _LC6_C12;
-- Node name is '|MINUTE1:2|:64'
-- Equation name is '_LC5_C9', type is buried
_LC5_C9 = LCELL( _EQ024);
_EQ024 = !_LC1_C9 & !_LC2_C9 & _LC6_C9 & _LC8_C9;
-- Node name is '|SECOND1:1|:31' = '|SECOND1:1|cq00'
-- Equation name is '_LC1_C17', type is buried
_LC1_C17 = DFFE(!_LC1_C17, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
-- Node name is '|SECOND1:1|:30' = '|SECOND1:1|cq01'
-- Equation name is '_LC4_C17', type is buried
_LC4_C17 = DFFE( _EQ025, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ025 = !_LC1_C17 & _LC4_C17 & !_LC8_C17
# _LC1_C17 & !_LC4_C17 & !_LC8_C17;
-- Node name is '|SECOND1:1|:29' = '|SECOND1:1|cq02'
-- Equation name is '_LC7_C17', type is buried
_LC7_C17 = DFFE( _EQ026, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ026 = !_LC4_C17 & _LC7_C17 & !_LC8_C17
# !_LC1_C17 & _LC7_C17 & !_LC8_C17
# _LC1_C17 & _LC4_C17 & !_LC7_C17 & !_LC8_C17;
-- Node name is '|SECOND1:1|:28' = '|SECOND1:1|cq03'
-- Equation name is '_LC5_C17', type is buried
_LC5_C17 = DFFE( _EQ027, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ027 = !_LC1_C17 & _LC5_C17
# _LC1_C17 & _LC4_C17 & !_LC5_C17 & _LC7_C17
# !_LC4_C17 & _LC5_C17 & _LC7_C17
# _LC4_C17 & _LC5_C17 & !_LC7_C17;
-- Node name is '|SECOND1:1|:27' = '|SECOND1:1|cq10'
-- Equation name is '_LC2_C17', type is buried
_LC2_C17 = DFFE( _EQ028, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ028 = _LC2_C17 & !_LC8_C17
# !_LC2_C17 & _LC8_C17;
-- Node name is '|SECOND1:1|:26' = '|SECOND1:1|cq11'
-- Equation name is '_LC3_C12', type is buried
_LC3_C12 = DFFE( _EQ029, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ029 = !_LC2_C17 & _LC3_C12 & !_LC4_C12
# _LC2_C17 & !_LC3_C12 & !_LC4_C12 & _LC8_C17
# _LC3_C12 & !_LC8_C17;
-- Node name is '|SECOND1:1|:25' = '|SECOND1:1|cq12'
-- Equation name is '_LC3_C17', type is buried
_LC3_C17 = DFFE( _EQ030, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ030 = _LC3_C17 & !_LC4_C12 & !_LC6_C17
# !_LC3_C17 & !_LC4_C12 & _LC6_C17 & _LC8_C17
# _LC3_C17 & !_LC8_C17;
-- Node name is '|SECOND1:1|:24' = '|SECOND1:1|cq13'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = DFFE( _EQ031, GLOBAL( CLK), GLOBAL(!RESET), VCC, VCC);
_EQ031 = !_LC4_C12 & _LC7_C12 & _LC8_C17
# _LC1_C12 & !_LC8_C17;
-- Node name is '|SECOND1:1|LPM_ADD_SUB:63|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C17', type is buried
_LC6_C17 = LCELL( _EQ032);
_EQ032 = _LC2_C17 & _LC3_C12;
-- Node name is '|SECOND1:1|LPM_ADD_SUB:63|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_C12', type is buried
_LC7_C12 = LCELL( _EQ033);
_EQ033 = _LC1_C12 & !_LC3_C12
# _LC1_C12 & !_LC2_C17
# _LC1_C12 & !_LC3_C17
# !_LC1_C12 & _LC2_C17 & _LC3_C12 & _LC3_C17;
-- Node name is '|SECOND1:1|:20'
-- Equation name is '_LC2_C12', type is buried
_LC2_C12 = DFFE( _EQ034, GLOBAL( CLK), VCC, VCC, !_LC3_C2);
_EQ034 = _LC4_C12 & _LC8_C17
# _LC2_C12 & !_LC8_C17;
-- Node name is '|SECOND1:1|:49'
-- Equation name is '_LC8_C17', type is buried
!_LC8_C17 = _LC8_C17~NOT;
_LC8_C17~NOT = LCELL( _EQ035);
_EQ035 = !_LC1_C17
# _LC4_C17
# !_LC5_C17
# _LC7_C17;
-- Node name is '|SECOND1:1|:64'
-- Equation name is '_LC4_C12', type is buried
_LC4_C12 = LCELL( _EQ036);
_EQ036 = !_LC1_C12 & _LC2_C17 & !_LC3_C12 & _LC3_C17;
Project Information c:\mp2student\clock5\shijian.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,540K
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