📄 shijian.rpt
字号:
55 - - C -- OUTPUT 0 1 0 0 MIN02
87 - - - 12 OUTPUT 0 1 0 0 MIN03
62 - - B -- OUTPUT 0 1 0 0 MIN10
71 - - A -- OUTPUT 0 1 0 0 MIN11
61 - - B -- OUTPUT 0 1 0 0 MIN12
47 - - - 09 OUTPUT 0 1 0 0 MIN13
30 - - - 18 OUTPUT 0 1 0 0 SEC00
21 - - C -- OUTPUT 0 1 0 0 SEC01
23 - - C -- OUTPUT 0 1 0 0 SEC02
15 - - B -- OUTPUT 0 1 0 0 SEC03
20 - - C -- OUTPUT 0 1 0 0 SEC10
45 - - - 11 OUTPUT 0 1 0 0 SEC11
57 - - C -- OUTPUT 0 1 0 0 SEC12
43 - - - 12 OUTPUT 0 1 0 0 SEC13
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\mp2student\clock5\shijian.rpt
shijian
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - C 02 AND2 0 2 0 1 |HOUR1:22|LPM_ADD_SUB:144|addcore:adder|:55
- 4 - C 05 DFFE 0 3 1 0 |HOUR1:22|:20
- 6 - C 02 DFFE 0 4 1 1 |HOUR1:22|cq13 (|HOUR1:22|:24)
- 1 - C 02 DFFE 0 4 1 2 |HOUR1:22|cq12 (|HOUR1:22|:25)
- 5 - C 02 DFFE 0 4 1 3 |HOUR1:22|cq11 (|HOUR1:22|:26)
- 4 - C 02 DFFE 0 2 1 4 |HOUR1:22|cq10 (|HOUR1:22|:27)
- 3 - C 05 DFFE 0 4 1 3 |HOUR1:22|cq03 (|HOUR1:22|:28)
- 7 - C 05 DFFE 0 4 1 4 |HOUR1:22|cq02 (|HOUR1:22|:29)
- 5 - C 05 DFFE 0 4 1 4 |HOUR1:22|cq01 (|HOUR1:22|:30)
- 2 - C 05 DFFE 0 1 1 5 |HOUR1:22|cq00 (|HOUR1:22|:31)
- 2 - C 02 OR2 s 0 3 0 1 |HOUR1:22|~69~1
- 8 - C 05 OR2 s 0 3 0 1 |HOUR1:22|~69~2
- 6 - C 05 OR2 ! 0 4 0 3 |HOUR1:22|:69
- 1 - C 05 AND2 0 4 0 4 |HOUR1:22|:135
- 4 - C 09 AND2 0 2 0 1 |MINUTE1:2|LPM_ADD_SUB:63|addcore:adder|:55
- 7 - C 09 OR2 0 4 0 1 |MINUTE1:2|LPM_ADD_SUB:63|addcore:adder|:69
- 8 - C 02 DFFE 0 4 0 9 |MINUTE1:2|:20
- 2 - C 09 DFFE 0 4 1 2 |MINUTE1:2|cq13 (|MINUTE1:2|:24)
- 8 - C 09 DFFE 0 4 1 2 |MINUTE1:2|cq12 (|MINUTE1:2|:25)
- 1 - C 09 DFFE 0 4 1 3 |MINUTE1:2|cq11 (|MINUTE1:2|:26)
- 6 - C 09 DFFE 0 2 1 4 |MINUTE1:2|cq10 (|MINUTE1:2|:27)
- 8 - C 12 DFFE 0 4 1 1 |MINUTE1:2|cq03 (|MINUTE1:2|:28)
- 6 - C 12 DFFE 0 4 1 2 |MINUTE1:2|cq02 (|MINUTE1:2|:29)
- 3 - C 09 DFFE 0 3 1 3 |MINUTE1:2|cq01 (|MINUTE1:2|:30)
- 1 - C 03 DFFE 0 1 1 4 |MINUTE1:2|cq00 (|MINUTE1:2|:31)
- 5 - C 12 OR2 ! 0 4 0 7 |MINUTE1:2|:49
- 5 - C 09 AND2 0 4 0 4 |MINUTE1:2|:64
- 3 - C 02 SOFT s ! 1 0 0 3 RESET~1
- 6 - C 17 AND2 0 2 0 1 |SECOND1:1|LPM_ADD_SUB:63|addcore:adder|:55
- 7 - C 12 OR2 0 4 0 1 |SECOND1:1|LPM_ADD_SUB:63|addcore:adder|:69
- 2 - C 12 DFFE + 0 3 0 9 |SECOND1:1|:20
- 1 - C 12 DFFE + 0 3 1 2 |SECOND1:1|cq13 (|SECOND1:1|:24)
- 3 - C 17 DFFE + 0 3 1 2 |SECOND1:1|cq12 (|SECOND1:1|:25)
- 3 - C 12 DFFE + 0 3 1 3 |SECOND1:1|cq11 (|SECOND1:1|:26)
- 2 - C 17 DFFE + 0 1 1 4 |SECOND1:1|cq10 (|SECOND1:1|:27)
- 5 - C 17 DFFE + 0 3 1 1 |SECOND1:1|cq03 (|SECOND1:1|:28)
- 7 - C 17 DFFE + 0 3 1 2 |SECOND1:1|cq02 (|SECOND1:1|:29)
- 4 - C 17 DFFE + 0 2 1 3 |SECOND1:1|cq01 (|SECOND1:1|:30)
- 1 - C 17 DFFE + 0 0 1 4 |SECOND1:1|cq00 (|SECOND1:1|:31)
- 8 - C 17 OR2 ! 0 4 0 7 |SECOND1:1|:49
- 4 - C 12 AND2 0 4 0 4 |SECOND1:1|:64
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\mp2student\clock5\shijian.rpt
shijian
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 1/ 96( 1%) 4/ 48( 8%) 1/ 48( 2%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
C: 16/ 96( 16%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\mp2student\clock5\shijian.rpt
shijian
** CLOCK SIGNALS **
Type Fan-out Name
DFF 10 |MINUTE1:2|:20
DFF 10 |SECOND1:1|:20
INPUT 9 CLK
Device-Specific Information: c:\mp2student\clock5\shijian.rpt
shijian
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 25 RESET
Device-Specific Information: c:\mp2student\clock5\shijian.rpt
shijian
** EQUATIONS **
CLK : INPUT;
RESET : INPUT;
-- Node name is 'HOUR00'
-- Equation name is 'HOUR00', type is output
HOUR00 = _LC2_C5;
-- Node name is 'HOUR01'
-- Equation name is 'HOUR01', type is output
HOUR01 = _LC5_C5;
-- Node name is 'HOUR02'
-- Equation name is 'HOUR02', type is output
HOUR02 = _LC7_C5;
-- Node name is 'HOUR03'
-- Equation name is 'HOUR03', type is output
HOUR03 = _LC3_C5;
-- Node name is 'HOUR10'
-- Equation name is 'HOUR10', type is output
HOUR10 = _LC4_C2;
-- Node name is 'HOUR11'
-- Equation name is 'HOUR11', type is output
HOUR11 = _LC5_C2;
-- Node name is 'HOUR12'
-- Equation name is 'HOUR12', type is output
HOUR12 = _LC1_C2;
-- Node name is 'HOUR13'
-- Equation name is 'HOUR13', type is output
HOUR13 = _LC6_C2;
-- Node name is 'INDAY'
-- Equation name is 'INDAY', type is output
INDAY = _LC4_C5;
-- Node name is 'MIN00'
-- Equation name is 'MIN00', type is output
MIN00 = _LC1_C3;
-- Node name is 'MIN01'
-- Equation name is 'MIN01', type is output
MIN01 = _LC3_C9;
-- Node name is 'MIN02'
-- Equation name is 'MIN02', type is output
MIN02 = _LC6_C12;
-- Node name is 'MIN03'
-- Equation name is 'MIN03', type is output
MIN03 = _LC8_C12;
-- Node name is 'MIN10'
-- Equation name is 'MIN10', type is output
MIN10 = _LC6_C9;
-- Node name is 'MIN11'
-- Equation name is 'MIN11', type is output
MIN11 = _LC1_C9;
-- Node name is 'MIN12'
-- Equation name is 'MIN12', type is output
MIN12 = _LC8_C9;
-- Node name is 'MIN13'
-- Equation name is 'MIN13', type is output
MIN13 = _LC2_C9;
-- Node name is 'RESET~1'
-- Equation name is 'RESET~1', location is LC3_C2, type is buried.
-- synthesized logic cell
!_LC3_C2 = _LC3_C2~NOT;
_LC3_C2~NOT = LCELL(!RESET);
-- Node name is 'SEC00'
-- Equation name is 'SEC00', type is output
SEC00 = _LC1_C17;
-- Node name is 'SEC01'
-- Equation name is 'SEC01', type is output
SEC01 = _LC4_C17;
-- Node name is 'SEC02'
-- Equation name is 'SEC02', type is output
SEC02 = _LC7_C17;
-- Node name is 'SEC03'
-- Equation name is 'SEC03', type is output
SEC03 = _LC5_C17;
-- Node name is 'SEC10'
-- Equation name is 'SEC10', type is output
SEC10 = _LC2_C17;
-- Node name is 'SEC11'
-- Equation name is 'SEC11', type is output
SEC11 = _LC3_C12;
-- Node name is 'SEC12'
-- Equation name is 'SEC12', type is output
SEC12 = _LC3_C17;
-- Node name is 'SEC13'
-- Equation name is 'SEC13', type is output
SEC13 = _LC1_C12;
-- Node name is '|HOUR1:22|:31' = '|HOUR1:22|cq00'
-- Equation name is '_LC2_C5', type is buried
_LC2_C5 = DFFE(!_LC2_C5, _LC8_C2, GLOBAL(!RESET), VCC, VCC);
-- Node name is '|HOUR1:22|:30' = '|HOUR1:22|cq01'
-- Equation name is '_LC5_C5', type is buried
_LC5_C5 = DFFE( _EQ001, _LC8_C2, GLOBAL(!RESET), VCC, VCC);
_EQ001 = !_LC2_C5 & _LC5_C5
# _LC2_C5 & !_LC3_C5 & !_LC5_C5
# _LC2_C5 & !_LC5_C5 & _LC7_C5;
-- Node name is '|HOUR1:22|:29' = '|HOUR1:22|cq02'
-- Equation name is '_LC7_C5', type is buried
_LC7_C5 = DFFE( _EQ002, _LC8_C2, GLOBAL(!RESET), VCC, VCC);
_EQ002 = _LC2_C5 & _LC5_C5 & !_LC7_C5
# _LC2_C5 & _LC5_C5 & _LC6_C5
# !_LC5_C5 & !_LC6_C5 & _LC7_C5
# !_LC2_C5 & !_LC6_C5 & _LC7_C5;
-- Node name is '|HOUR1:22|:28' = '|HOUR1:22|cq03'
-- Equation name is '_LC3_C5', type is buried
_LC3_C5 = DFFE( _EQ003, _LC8_C2, GLOBAL(!RESET), VCC, VCC);
_EQ003 = _LC2_C5 & !_LC3_C5 & _LC5_C5 & _LC7_C5
# !_LC2_C5 & _LC3_C5
# _LC3_C5 & !_LC5_C5 & _LC7_C5
# _LC3_C5 & _LC5_C5 & !_LC7_C5;
-- Node name is '|HOUR1:22|:27' = '|HOUR1:22|cq10'
-- Equation name is '_LC4_C2', type is buried
_LC4_C2 = DFFE( _EQ004, _LC8_C2, GLOBAL(!RESET), VCC, VCC);
_EQ004 = !_LC1_C5 & _LC4_C2
# _LC1_C5 & !_LC4_C2;
-- Node name is '|HOUR1:22|:26' = '|HOUR1:22|cq11'
-- Equation name is '_LC5_C2', type is buried
_LC5_C2 = DFFE( _EQ005, _LC8_C2, GLOBAL(!RESET), VCC, VCC);
_EQ005 = !_LC1_C5 & _LC5_C2 & !_LC6_C5
# _LC1_C5 & !_LC4_C2 & _LC5_C2
# _LC1_C5 & _LC4_C2 & !_LC5_C2;
-- Node name is '|HOUR1:22|:25' = '|HOUR1:22|cq12'
-- Equation name is '_LC1_C2', type is buried
_LC1_C2 = DFFE( _EQ006, _LC8_C2, GLOBAL(!RESET), VCC, VCC);
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