📄 month1.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\mp2student\clock5\month1.rpt
month1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 10/ 96( 10%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\mp2student\clock5\month1.rpt
month1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clkd
Device-Specific Information: e:\mp2student\clock5\month1.rpt
month1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 reset
Device-Specific Information: e:\mp2student\clock5\month1.rpt
month1
** EQUATIONS **
clkd : INPUT;
reset : INPUT;
-- Node name is ':31' = 'cq00'
-- Equation name is 'cq00', location is LC6_A2, type is buried.
cq00 = DFFE( _EQ001, GLOBAL( clkd), GLOBAL(!reset), VCC, VCC);
_EQ001 = _LC3_A2
# !cq00 & !_LC7_A2;
-- Node name is ':30' = 'cq01'
-- Equation name is 'cq01', location is LC1_A2, type is buried.
cq01 = DFFE( _EQ002, GLOBAL( clkd), GLOBAL(!reset), VCC, VCC);
_EQ002 = !cq00 & cq01 & !_LC3_A2
# !_LC3_A2 & _LC7_A2
# cq00 & !cq01 & !_LC3_A2;
-- Node name is ':29' = 'cq02'
-- Equation name is 'cq02', location is LC8_A2, type is buried.
cq02 = DFFE( _EQ003, GLOBAL( clkd), GLOBAL(!reset), VCC, VCC);
_EQ003 = !cq01 & cq02 & !_LC3_A2
# !cq00 & cq02 & !_LC3_A2
# cq00 & cq01 & !cq02 & !_LC3_A2;
-- Node name is ':28' = 'cq03'
-- Equation name is 'cq03', location is LC2_A2, type is buried.
cq03 = DFFE( _EQ004, GLOBAL( clkd), GLOBAL(!reset), VCC, VCC);
_EQ004 = !cq00 & cq03
# cq00 & cq01 & cq02 & !cq03
# !cq01 & cq02 & cq03
# cq01 & !cq02 & cq03;
-- Node name is ':27' = 'cq10'
-- Equation name is 'cq10', location is LC5_A5, type is buried.
cq10 = DFFE( _EQ005, GLOBAL( clkd), GLOBAL(!reset), VCC, VCC);
_EQ005 = !cq10 & _LC3_A2
# cq10 & !_LC3_A2 & !_LC7_A2;
-- Node name is ':26' = 'cq11'
-- Equation name is 'cq11', location is LC1_A5, type is buried.
cq11 = DFFE( _EQ006, GLOBAL( clkd), GLOBAL(!reset), VCC, VCC);
_EQ006 = !cq10 & cq11
# cq10 & !cq11 & _LC3_A2
# cq11 & !_LC3_A2;
-- Node name is ':25' = 'cq12'
-- Equation name is 'cq12', location is LC8_A5, type is buried.
cq12 = DFFE( _EQ007, GLOBAL( clkd), GLOBAL(!reset), VCC, VCC);
_EQ007 = !cq11 & cq12
# !cq10 & cq12
# cq10 & cq11 & !cq12 & _LC3_A2
# cq12 & !_LC3_A2;
-- Node name is ':24' = 'cq13'
-- Equation name is 'cq13', location is LC2_A5, type is buried.
cq13 = DFFE( _EQ008, GLOBAL( clkd), GLOBAL(!reset), VCC, VCC);
_EQ008 = cq13 & !_LC4_A5
# !cq12 & cq13
# cq12 & !cq13 & _LC3_A2 & _LC4_A5
# cq13 & !_LC3_A2;
-- Node name is 'enyear'
-- Equation name is 'enyear', type is output
enyear = _LC3_A5;
-- Node name is 'month00'
-- Equation name is 'month00', type is output
month00 = cq00;
-- Node name is 'month01'
-- Equation name is 'month01', type is output
month01 = cq01;
-- Node name is 'month02'
-- Equation name is 'month02', type is output
month02 = cq02;
-- Node name is 'month03'
-- Equation name is 'month03', type is output
month03 = cq03;
-- Node name is 'month10'
-- Equation name is 'month10', type is output
month10 = cq10;
-- Node name is 'month11'
-- Equation name is 'month11', type is output
month11 = cq11;
-- Node name is 'month12'
-- Equation name is 'month12', type is output
month12 = cq12;
-- Node name is 'month13'
-- Equation name is 'month13', type is output
month13 = cq13;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC7_A5, type is buried.
-- synthesized logic cell
!_LC7_A5 = _LC7_A5~NOT;
_LC7_A5~NOT = LCELL(!reset);
-- Node name is '|LPM_ADD_SUB:144|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A5', type is buried
_LC4_A5 = LCELL( _EQ009);
_EQ009 = cq10 & cq11;
-- Node name is ':20'
-- Equation name is '_LC3_A5', type is buried
_LC3_A5 = DFFE( _LC7_A2, GLOBAL( clkd), VCC, VCC, !_LC7_A5);
-- Node name is '~69~1'
-- Equation name is '~69~1', location is LC4_A2, type is buried.
-- synthesized logic cell
_LC4_A2 = LCELL( _EQ010);
_EQ010 = cq02
# !cq01
# cq00;
-- Node name is '~69~2'
-- Equation name is '~69~2', location is LC6_A5, type is buried.
-- synthesized logic cell
_LC6_A5 = LCELL( _EQ011);
_EQ011 = cq12
# cq11
# !cq10;
-- Node name is ':69'
-- Equation name is '_LC7_A2', type is buried
!_LC7_A2 = _LC7_A2~NOT;
_LC7_A2~NOT = LCELL( _EQ012);
_EQ012 = cq03
# _LC4_A2
# cq13
# _LC6_A5;
-- Node name is ':135'
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = LCELL( _EQ013);
_EQ013 = cq00 & !cq01 & !cq02 & cq03;
Project Information e:\mp2student\clock5\month1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,772K
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