📄 myclock.rpt
字号:
- 1 - F 17 OR2 2 1 1 0 :585
- 3 - F 01 OR2 2 1 1 0 :594
- 6 - F 32 OR2 2 2 1 0 :603
- 5 - F 32 OR2 2 2 1 0 :612
- 3 - F 32 OR2 2 2 1 0 :621
- 1 - F 32 OR2 2 2 1 0 :630
- 1 - F 08 OR2 2 2 1 0 :639
- 1 - F 09 OR2 2 2 1 0 :648
- 4 - F 27 OR2 2 2 1 0 :657
- 1 - F 31 OR2 2 2 1 0 :666
- 6 - F 03 OR2 2 2 1 0 :675
- 1 - F 05 OR2 2 2 1 0 :684
- 6 - F 06 OR2 2 2 1 0 :693
- 8 - F 08 OR2 2 2 1 0 :702
- 4 - F 02 OR2 2 2 1 0 :711
- 5 - F 02 OR2 2 2 1 0 :720
- 8 - F 02 OR2 2 2 1 0 :729
- 3 - F 02 OR2 2 2 1 0 :738
- 4 - F 04 OR2 2 2 1 0 :747
- 8 - F 04 OR2 2 2 1 0 :756
- 1 - F 04 OR2 2 2 1 0 :765
- 1 - F 02 OR2 2 2 1 0 :774
- 5 - F 09 OR2 2 2 1 0 :783
- 6 - F 09 OR2 2 2 1 0 :792
- 8 - F 07 OR2 2 2 1 0 :801
- 1 - F 07 OR2 2 2 1 0 :810
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: l:\mp2student\clock5\myclock.rpt
myclock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 2/144( 1%) 2/ 72( 2%) 0/ 72( 0%) 3/16( 18%) 2/16( 12%) 0/16( 0%)
D: 1/144( 0%) 5/ 72( 6%) 0/ 72( 0%) 1/16( 6%) 5/16( 31%) 0/16( 0%)
E: 0/144( 0%) 3/ 72( 4%) 0/ 72( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
F: 33/144( 22%) 27/ 72( 37%) 10/ 72( 13%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: l:\mp2student\clock5\myclock.rpt
myclock
** CLOCK SIGNALS **
Type Fan-out Name
DFF 13 |hour1:u3|:20
DFF 10 |minute1:u2|:20
DFF 10 |second1:u1|:20
INPUT 9 clk
DFF 9 |day1:u5|:20
DFF 8 |month1:u6|:20
Device-Specific Information: l:\mp2student\clock5\myclock.rpt
myclock
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 53 reset
Device-Specific Information: l:\mp2student\clock5\myclock.rpt
myclock
** EQUATIONS **
clk : INPUT;
en0 : INPUT;
en1 : INPUT;
reset : INPUT;
set : INPUT;
-- Node name is 'b00'
-- Equation name is 'b00', type is output
b00 = _LC1_F32;
-- Node name is 'b01'
-- Equation name is 'b01', type is output
b01 = _LC3_F32;
-- Node name is 'b02'
-- Equation name is 'b02', type is output
b02 = _LC5_F32;
-- Node name is 'b03'
-- Equation name is 'b03', type is output
b03 = _LC6_F32;
-- Node name is 'b10'
-- Equation name is 'b10', type is output
b10 = _LC1_F31;
-- Node name is 'b11'
-- Equation name is 'b11', type is output
b11 = _LC4_F27;
-- Node name is 'b12'
-- Equation name is 'b12', type is output
b12 = _LC1_F9;
-- Node name is 'b13'
-- Equation name is 'b13', type is output
b13 = _LC1_F8;
-- Node name is 'b20'
-- Equation name is 'b20', type is output
b20 = _LC8_F8;
-- Node name is 'b21'
-- Equation name is 'b21', type is output
b21 = _LC6_F6;
-- Node name is 'b22'
-- Equation name is 'b22', type is output
b22 = _LC1_F5;
-- Node name is 'b23'
-- Equation name is 'b23', type is output
b23 = _LC6_F3;
-- Node name is 'b30'
-- Equation name is 'b30', type is output
b30 = _LC3_F2;
-- Node name is 'b31'
-- Equation name is 'b31', type is output
b31 = _LC8_F2;
-- Node name is 'b32'
-- Equation name is 'b32', type is output
b32 = _LC5_F2;
-- Node name is 'b33'
-- Equation name is 'b33', type is output
b33 = _LC4_F2;
-- Node name is 'b40'
-- Equation name is 'b40', type is output
b40 = _LC1_F2;
-- Node name is 'b41'
-- Equation name is 'b41', type is output
b41 = _LC1_F4;
-- Node name is 'b42'
-- Equation name is 'b42', type is output
b42 = _LC8_F4;
-- Node name is 'b43'
-- Equation name is 'b43', type is output
b43 = _LC4_F4;
-- Node name is 'b50'
-- Equation name is 'b50', type is output
b50 = _LC1_F7;
-- Node name is 'b51'
-- Equation name is 'b51', type is output
b51 = _LC8_F7;
-- Node name is 'b52'
-- Equation name is 'b52', type is output
b52 = _LC6_F9;
-- Node name is 'b53'
-- Equation name is 'b53', type is output
b53 = _LC5_F9;
-- Node name is 'b60'
-- Equation name is 'b60', type is output
b60 = _LC3_F1;
-- Node name is 'b61'
-- Equation name is 'b61', type is output
b61 = _LC1_F17;
-- Node name is 'b62'
-- Equation name is 'b62', type is output
b62 = _LC7_F12;
-- Node name is 'b63'
-- Equation name is 'b63', type is output
b63 = _LC4_F12;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC4_F20, type is buried.
-- synthesized logic cell
!_LC4_F20 = _LC4_F20~NOT;
_LC4_F20~NOT = LCELL(!reset);
-- Node name is '|day1:u5|:31' = '|day1:u5|cq00'
-- Equation name is '_LC5_F31', type is buried
!_LC5_F31 = _LC5_F31~NOT;
_LC5_F31~NOT = DFFE( _EQ001, _LC3_F13, !reset, VCC, VCC);
_EQ001 = !_LC4_F5 & _LC5_F31
# _LC2_F31;
-- Node name is '|day1:u5|:30' = '|day1:u5|cq01'
-- Equation name is '_LC3_F31', type is buried
_LC3_F31 = DFFE( _EQ002, _LC3_F13, !reset, VCC, VCC);
_EQ002 = !_LC2_F31 & _LC3_F31 & !_LC5_F31
# !_LC2_F31 & _LC3_F31 & _LC4_F5
# !_LC2_F31 & !_LC3_F31 & !_LC4_F5 & _LC5_F31;
-- Node name is '|day1:u5|:29' = '|day1:u5|cq02'
-- Equation name is '_LC8_F31', type is buried
_LC8_F31 = DFFE( _EQ003, _LC3_F13, !reset, VCC, VCC);
_EQ003 = !_LC3_F31 & _LC8_F31
# !_LC5_F31 & _LC8_F31
# _LC3_F31 & _LC5_F31 & !_LC8_F31;
-- Node name is '|day1:u5|:28' = '|day1:u5|cq03'
-- Equation name is '_LC4_F31', type is buried
_LC4_F31 = DFFE( _EQ004, _LC3_F13, !reset, VCC, VCC);
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