📄 myclock.rpt
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Project Information l:\mp2student\clock5\myclock.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 06/29/2007 13:08:26
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
MYCLOCK
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
myclock EP1K30TC144-3 5 28 0 0 0 % 113 6 %
User Pins: 5 28 0
Project Information l:\mp2student\clock5\myclock.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Ignored unnecessary INPUT pin 'a03'
Warning: Ignored unnecessary INPUT pin 'a02'
Warning: Ignored unnecessary INPUT pin 'a01'
Warning: Ignored unnecessary INPUT pin 'a00'
Warning: Ignored unnecessary INPUT pin 'a13'
Warning: Ignored unnecessary INPUT pin 'a12'
Warning: Ignored unnecessary INPUT pin 'a11'
Warning: Ignored unnecessary INPUT pin 'a10'
Warning: Ignored unnecessary INPUT pin 'a23'
Warning: Ignored unnecessary INPUT pin 'a22'
Warning: Ignored unnecessary INPUT pin 'a21'
Warning: Ignored unnecessary INPUT pin 'a20'
Warning: Ignored unnecessary INPUT pin 'a33'
Warning: Ignored unnecessary INPUT pin 'a32'
Warning: Ignored unnecessary INPUT pin 'a31'
Warning: Ignored unnecessary INPUT pin 'a30'
Warning: Ignored unnecessary INPUT pin 'a43'
Warning: Ignored unnecessary INPUT pin 'a42'
Warning: Ignored unnecessary INPUT pin 'a41'
Warning: Ignored unnecessary INPUT pin 'a40'
Warning: Ignored unnecessary INPUT pin 'a53'
Warning: Ignored unnecessary INPUT pin 'a52'
Warning: Ignored unnecessary INPUT pin 'a51'
Warning: Ignored unnecessary INPUT pin 'a50'
Warning: Ignored unnecessary INPUT pin 'a63'
Warning: Ignored unnecessary INPUT pin 'a62'
Warning: Ignored unnecessary INPUT pin 'a61'
Warning: Ignored unnecessary INPUT pin 'a60'
Info: Reserved unused input pin 'set' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Project Information l:\mp2student\clock5\myclock.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
myclock@30 b00
myclock@31 b01
myclock@32 b02
myclock@33 b03
myclock@41 b10
myclock@42 b11
myclock@65 b12
myclock@67 b13
myclock@68 b20
myclock@69 b21
myclock@70 b22
myclock@72 b23
myclock@73 b30
myclock@78 b31
myclock@79 b32
myclock@80 b33
myclock@81 b40
myclock@82 b41
myclock@83 b42
myclock@86 b43
myclock@87 b50
myclock@88 b51
myclock@89 b52
myclock@90 b53
myclock@91 b60
myclock@92 b61
myclock@95 b62
myclock@96 b63
myclock@126 clk
myclock@13 en0
myclock@17 en1
myclock@19 reset
myclock@18 set
Project Information l:\mp2student\clock5\myclock.rpt
** FILE HIERARCHY **
|second1:u1|
|second1:u1|lpm_add_sub:48|
|second1:u1|lpm_add_sub:48|addcore:adder|
|second1:u1|lpm_add_sub:48|altshift:result_ext_latency_ffs|
|second1:u1|lpm_add_sub:48|altshift:carry_ext_latency_ffs|
|second1:u1|lpm_add_sub:48|altshift:oflow_ext_latency_ffs|
|second1:u1|lpm_add_sub:63|
|second1:u1|lpm_add_sub:63|addcore:adder|
|second1:u1|lpm_add_sub:63|altshift:result_ext_latency_ffs|
|second1:u1|lpm_add_sub:63|altshift:carry_ext_latency_ffs|
|second1:u1|lpm_add_sub:63|altshift:oflow_ext_latency_ffs|
|minute1:u2|
|minute1:u2|lpm_add_sub:48|
|minute1:u2|lpm_add_sub:48|addcore:adder|
|minute1:u2|lpm_add_sub:48|altshift:result_ext_latency_ffs|
|minute1:u2|lpm_add_sub:48|altshift:carry_ext_latency_ffs|
|minute1:u2|lpm_add_sub:48|altshift:oflow_ext_latency_ffs|
|minute1:u2|lpm_add_sub:63|
|minute1:u2|lpm_add_sub:63|addcore:adder|
|minute1:u2|lpm_add_sub:63|altshift:result_ext_latency_ffs|
|minute1:u2|lpm_add_sub:63|altshift:carry_ext_latency_ffs|
|minute1:u2|lpm_add_sub:63|altshift:oflow_ext_latency_ffs|
|hour1:u3|
|hour1:u3|lpm_add_sub:134|
|hour1:u3|lpm_add_sub:134|addcore:adder|
|hour1:u3|lpm_add_sub:134|altshift:result_ext_latency_ffs|
|hour1:u3|lpm_add_sub:134|altshift:carry_ext_latency_ffs|
|hour1:u3|lpm_add_sub:134|altshift:oflow_ext_latency_ffs|
|hour1:u3|lpm_add_sub:144|
|hour1:u3|lpm_add_sub:144|addcore:adder|
|hour1:u3|lpm_add_sub:144|altshift:result_ext_latency_ffs|
|hour1:u3|lpm_add_sub:144|altshift:carry_ext_latency_ffs|
|hour1:u3|lpm_add_sub:144|altshift:oflow_ext_latency_ffs|
|week1:u4|
|week1:u4|lpm_add_sub:28|
|week1:u4|lpm_add_sub:28|addcore:adder|
|week1:u4|lpm_add_sub:28|altshift:result_ext_latency_ffs|
|week1:u4|lpm_add_sub:28|altshift:carry_ext_latency_ffs|
|week1:u4|lpm_add_sub:28|altshift:oflow_ext_latency_ffs|
|day1:u5|
|day1:u5|lpm_add_sub:134|
|day1:u5|lpm_add_sub:134|addcore:adder|
|day1:u5|lpm_add_sub:134|altshift:result_ext_latency_ffs|
|day1:u5|lpm_add_sub:134|altshift:carry_ext_latency_ffs|
|day1:u5|lpm_add_sub:134|altshift:oflow_ext_latency_ffs|
|day1:u5|lpm_add_sub:144|
|day1:u5|lpm_add_sub:144|addcore:adder|
|day1:u5|lpm_add_sub:144|altshift:result_ext_latency_ffs|
|day1:u5|lpm_add_sub:144|altshift:carry_ext_latency_ffs|
|day1:u5|lpm_add_sub:144|altshift:oflow_ext_latency_ffs|
|month1:u6|
|month1:u6|lpm_add_sub:134|
|month1:u6|lpm_add_sub:134|addcore:adder|
|month1:u6|lpm_add_sub:134|altshift:result_ext_latency_ffs|
|month1:u6|lpm_add_sub:134|altshift:carry_ext_latency_ffs|
|month1:u6|lpm_add_sub:134|altshift:oflow_ext_latency_ffs|
|month1:u6|lpm_add_sub:144|
|month1:u6|lpm_add_sub:144|addcore:adder|
|month1:u6|lpm_add_sub:144|altshift:result_ext_latency_ffs|
|month1:u6|lpm_add_sub:144|altshift:carry_ext_latency_ffs|
|month1:u6|lpm_add_sub:144|altshift:oflow_ext_latency_ffs|
|year1:u7|
|year1:u7|lpm_add_sub:44|
|year1:u7|lpm_add_sub:44|addcore:adder|
|year1:u7|lpm_add_sub:44|altshift:result_ext_latency_ffs|
|year1:u7|lpm_add_sub:44|altshift:carry_ext_latency_ffs|
|year1:u7|lpm_add_sub:44|altshift:oflow_ext_latency_ffs|
|year1:u7|lpm_add_sub:59|
|year1:u7|lpm_add_sub:59|addcore:adder|
|year1:u7|lpm_add_sub:59|altshift:result_ext_latency_ffs|
|year1:u7|lpm_add_sub:59|altshift:carry_ext_latency_ffs|
|year1:u7|lpm_add_sub:59|altshift:oflow_ext_latency_ffs|
Device-Specific Information: l:\mp2student\clock5\myclock.rpt
myclock
***** Logic for device 'myclock' compiled without errors.
Device: EP1K30TC144-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S S V S S S S S S S S S S S S S
E E E E E E E E E V E E E E E C E E E E E E E V E E E E E E
R R R R R R R R R C R R R R R C R R R R R R R C R R R R R R
V V V V V G V V V V C V V V V G V I c G G G V V V V V V V C V V V V V V
E E E E E N E E E E I E E E E N E N l N N N E E E E E E E I E E E E E E
D D D D D D D D D D O D D D D D D T k D D D D D D D D D D O D D D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GND
GND | 6 103 | VCCINT
RESERVED | 7 102 | RESERVED
RESERVED | 8 101 | RESERVED
RESERVED | 9 100 | RESERVED
RESERVED | 10 99 | RESERVED
RESERVED | 11 98 | RESERVED
RESERVED | 12 97 | RESERVED
en0 | 13 96 | b63
RESERVED | 14 95 | b62
GND | 15 94 | VCCIO
VCCINT | 16 93 | GND
en1 | 17 92 | b61
set | 18 91 | b60
reset | 19 EP1K30TC144-3 90 | b53
RESERVED | 20 89 | b52
RESERVED | 21 88 | b51
RESERVED | 22 87 | b50
RESERVED | 23 86 | b43
VCCIO | 24 85 | VCCINT
GND | 25 84 | GND
RESERVED | 26 83 | b42
RESERVED | 27 82 | b41
RESERVED | 28 81 | b40
RESERVED | 29 80 | b33
b00 | 30 79 | b32
b01 | 31 78 | b31
b02 | 32 77 | ^MSEL0
b03 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | b30
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
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