fenlu.rpt

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-- Node name is 'reset~23' 
-- Equation name is 'reset~23', location is LC1_B4, type is buried.
-- synthesized logic cell 
_LC1_B4  = LCELL( _EQ052);
  _EQ052 =  b12 & !en0 & !en1;

-- Node name is 'reset~24' 
-- Equation name is 'reset~24', location is LC5_B4, type is buried.
-- synthesized logic cell 
_LC5_B4  = LCELL( _EQ053);
  _EQ053 =  b13 & !en0 & !en1;

-- Node name is 'reset~25' 
-- Equation name is 'reset~25', location is LC7_A21, type is buried.
-- synthesized logic cell 
_LC7_A21 = LCELL( _EQ054);
  _EQ054 =  b00 & !en0 & !en1;

-- Node name is 'reset~26' 
-- Equation name is 'reset~26', location is LC6_C17, type is buried.
-- synthesized logic cell 
_LC6_C17 = LCELL( _EQ055);
  _EQ055 =  b01 & !en0 & !en1;

-- Node name is 'reset~27' 
-- Equation name is 'reset~27', location is LC4_A17, type is buried.
-- synthesized logic cell 
_LC4_A17 = LCELL( _EQ056);
  _EQ056 =  b02 & !en0 & !en1;

-- Node name is '~216~1' 
-- Equation name is '~216~1', location is LC2_B9, type is buried.
-- synthesized logic cell 
_LC2_B9  = LCELL( _EQ057);
  _EQ057 =  en0 &  en1;

-- Node name is '~838~1' 
-- Equation name is '~838~1', location is LC8_C5, type is buried.
-- synthesized logic cell 
_LC8_C5  = LCELL( _EQ058);
  _EQ058 =  c03 &  _LC2_B9 &  set
         #  _LC6_C5 &  set;

-- Node name is '~844~1' 
-- Equation name is '~844~1', location is LC7_A17, type is buried.
-- synthesized logic cell 
_LC7_A17 = LCELL( _EQ059);
  _EQ059 =  c02 &  _LC2_B9 &  set
         #  _LC4_A17 &  set;

-- Node name is '~850~1' 
-- Equation name is '~850~1', location is LC7_C17, type is buried.
-- synthesized logic cell 
_LC7_C17 = LCELL( _EQ060);
  _EQ060 =  c01 &  _LC2_B9 &  set
         #  _LC6_C17 &  set;

-- Node name is '~856~1' 
-- Equation name is '~856~1', location is LC8_A21, type is buried.
-- synthesized logic cell 
_LC8_A21 = LCELL( _EQ061);
  _EQ061 =  c00 &  _LC2_B9 &  set
         #  _LC7_A21 &  set;

-- Node name is '~862~1' 
-- Equation name is '~862~1', location is LC6_B4, type is buried.
-- synthesized logic cell 
_LC6_B4  = LCELL( _EQ062);
  _EQ062 =  c13 &  _LC2_B9 &  set
         #  _LC5_B4 &  set;

-- Node name is '~868~1' 
-- Equation name is '~868~1', location is LC3_B4, type is buried.
-- synthesized logic cell 
_LC3_B4  = LCELL( _EQ063);
  _EQ063 =  c12 &  _LC2_B9 &  set
         #  _LC1_B4 &  set;

-- Node name is '~874~1' 
-- Equation name is '~874~1', location is LC8_A13, type is buried.
-- synthesized logic cell 
_LC8_A13 = LCELL( _EQ064);
  _EQ064 =  c11 &  _LC2_B9 &  set
         #  _LC1_A16 &  set;

-- Node name is '~880~1' 
-- Equation name is '~880~1', location is LC7_A13, type is buried.
-- synthesized logic cell 
_LC7_A13 = LCELL( _EQ065);
  _EQ065 =  c10 &  _LC2_B9 &  set
         #  _LC4_A13 &  set;

-- Node name is '~886~1' 
-- Equation name is '~886~1', location is LC3_A13, type is buried.
-- synthesized logic cell 
_LC3_A13 = LCELL( _EQ066);
  _EQ066 =  c23 &  _LC2_B9 &  set
         #  _LC2_A13 &  set;

-- Node name is '~892~1' 
-- Equation name is '~892~1', location is LC8_B2, type is buried.
-- synthesized logic cell 
_LC8_B2  = LCELL( _EQ067);
  _EQ067 =  c22 &  _LC2_B9 &  set
         #  _LC7_B2 &  set;

-- Node name is '~898~1' 
-- Equation name is '~898~1', location is LC6_B2, type is buried.
-- synthesized logic cell 
_LC6_B2  = LCELL( _EQ068);
  _EQ068 =  c21 &  _LC2_B9 &  set
         #  _LC5_B2 &  set;

-- Node name is '~904~1' 
-- Equation name is '~904~1', location is LC1_B2, type is buried.
-- synthesized logic cell 
_LC1_B2  = LCELL( _EQ069);
  _EQ069 =  c20 &  _LC2_B9 &  set
         #  _LC4_B2 &  set;

-- Node name is '~910~1' 
-- Equation name is '~910~1', location is LC5_C5, type is buried.
-- synthesized logic cell 
_LC5_C5  = LCELL( _EQ070);
  _EQ070 =  c33 &  _LC2_B9 &  set
         #  _LC2_A16 &  set;

-- Node name is '~916~1' 
-- Equation name is '~916~1', location is LC3_C5, type is buried.
-- synthesized logic cell 
_LC3_C5  = LCELL( _EQ071);
  _EQ071 =  c32 &  _LC2_B9 &  set
         #  _LC2_C5 &  set;

-- Node name is '~922~1' 
-- Equation name is '~922~1', location is LC3_A17, type is buried.
-- synthesized logic cell 
_LC3_A17 = LCELL( _EQ072);
  _EQ072 =  c31 &  _LC2_B9 &  set
         #  _LC3_A16 &  set;

-- Node name is '~928~1' 
-- Equation name is '~928~1', location is LC2_A17, type is buried.
-- synthesized logic cell 
_LC2_A17 = LCELL( _EQ073);
  _EQ073 =  c30 &  _LC2_B9 &  set
         #  _LC1_A17 &  set;

-- Node name is '~934~1' 
-- Equation name is '~934~1', location is LC7_B7, type is buried.
-- synthesized logic cell 
_LC7_B7  = LCELL( _EQ074);
  _EQ074 =  c43 &  _LC2_B9 &  set
         #  _LC6_B7 &  set;

-- Node name is '~940~1' 
-- Equation name is '~940~1', location is LC5_C17, type is buried.
-- synthesized logic cell 
_LC5_C17 = LCELL( _EQ075);
  _EQ075 =  c42 &  _LC2_B9 &  set
         #  _LC8_A16 &  set;

-- Node name is '~946~1' 
-- Equation name is '~946~1', location is LC4_C17, type is buried.
-- synthesized logic cell 
_LC4_C17 = LCELL( _EQ076);
  _EQ076 =  c41 &  _LC2_B9 &  set
         #  _LC3_C17 &  set;

-- Node name is '~952~1' 
-- Equation name is '~952~1', location is LC6_A21, type is buried.
-- synthesized logic cell 
_LC6_A21 = LCELL( _EQ077);
  _EQ077 =  c40 &  _LC2_B9 &  set
         #  _LC4_A16 &  set;

-- Node name is '~958~1' 
-- Equation name is '~958~1', location is LC5_A21, type is buried.
-- synthesized logic cell 
_LC5_A21 = LCELL( _EQ078);
  _EQ078 =  c53 &  _LC2_B9 &  set
         #  _LC4_A21 &  set;

-- Node name is '~964~1' 
-- Equation name is '~964~1', location is LC5_B7, type is buried.
-- synthesized logic cell 
_LC5_B7  = LCELL( _EQ079);
  _EQ079 =  c52 &  _LC2_B9 &  set
         #  _LC6_A16 &  set;

-- Node name is '~970~1' 
-- Equation name is '~970~1', location is LC4_B7, type is buried.
-- synthesized logic cell 
_LC4_B7  = LCELL( _EQ080);
  _EQ080 =  c51 &  _LC2_B9 &  set
         #  _LC3_B7 &  set;

-- Node name is '~976~1' 
-- Equation name is '~976~1', location is LC8_A15, type is buried.
-- synthesized logic cell 
_LC8_A15 = LCELL( _EQ081);
  _EQ081 =  c50 &  _LC2_B9 &  set
         #  _LC6_A15 &  set;

-- Node name is '~982~1' 
-- Equation name is '~982~1', location is LC5_A15, type is buried.
-- synthesized logic cell 
_LC5_A15 = LCELL( _EQ082);
  _EQ082 =  c63 &  _LC2_B9 &  set
         #  _LC5_A16 &  set;

-- Node name is '~988~1' 
-- Equation name is '~988~1', location is LC4_A15, type is buried.
-- synthesized logic cell 
_LC4_A15 = LCELL( _EQ083);
  _EQ083 =  c62 &  _LC2_B9 &  set
         #  _LC2_A15 &  set;

-- Node name is '~994~1' 
-- Equation name is '~994~1', location is LC7_B9, type is buried.
-- synthesized logic cell 
_LC7_B9  = LCELL( _EQ084);
  _EQ084 =  c61 &  _LC2_B9 &  set
         #  _LC6_B9 &  set;

-- Node name is '~1000~1' 
-- Equation name is '~1000~1', location is LC1_B9, type is buried.
-- synthesized logic cell 
_LC1_B9  = LCELL( _EQ085);
  _EQ085 =  en0 & !en1
         # !en0 &  en1
         # !set;

-- Node name is '~1000~2' 
-- Equation name is '~1000~2', location is LC5_B9, type is buried.
-- synthesized logic cell 
_LC5_B9  = LCELL( _EQ086);
  _EQ086 =  c60 &  _LC2_B9 &  set
         #  _LC3_B9 &  set;



Project Information                                         c:\clock\fenlu.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 18,000K