📄 fenlu.rpt
字号:
9 - - A -- OUTPUT 0 1 0 0 d50
86 - - B -- OUTPUT 0 1 0 0 d51
91 - - B -- OUTPUT 0 1 0 0 d52
39 - - - 21 OUTPUT 0 1 0 0 d53
121 - - - 10 OUTPUT 0 1 0 0 d60
65 - - - 09 OUTPUT 0 1 0 0 d61
47 - - - 16 OUTPUT 0 1 0 0 d62
7 - - A -- OUTPUT 0 1 0 0 d63
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\clock\fenlu.rpt
fenlu
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - C 05 AND2 s 3 0 0 1 b03~1
- 3 - B 09 AND2 s 3 0 0 1 reset~1
- 6 - B 09 AND2 s 3 0 0 1 reset~2
- 2 - A 15 AND2 s 3 0 0 1 reset~3
- 5 - A 16 AND2 s 3 0 0 1 reset~4
- 6 - A 15 AND2 s 3 0 0 1 reset~5
- 3 - B 07 AND2 s 3 0 0 1 reset~6
- 6 - A 16 AND2 s 3 0 0 1 reset~7
- 4 - A 21 AND2 s 3 0 0 1 reset~8
- 4 - A 16 AND2 s 3 0 0 1 reset~9
- 3 - C 17 AND2 s 3 0 0 1 reset~10
- 8 - A 16 AND2 s 3 0 0 1 reset~11
- 6 - B 07 AND2 s 3 0 0 1 reset~12
- 1 - A 17 AND2 s 3 0 0 1 reset~13
- 3 - A 16 AND2 s 3 0 0 1 reset~14
- 2 - C 05 AND2 s 3 0 0 1 reset~15
- 2 - A 16 AND2 s 3 0 0 1 reset~16
- 4 - B 02 AND2 s 3 0 0 1 reset~17
- 5 - B 02 AND2 s 3 0 0 1 reset~18
- 7 - B 02 AND2 s 3 0 0 1 reset~19
- 2 - A 13 AND2 s 3 0 0 1 reset~20
- 4 - A 13 AND2 s 3 0 0 1 reset~21
- 1 - A 16 AND2 s 3 0 0 1 reset~22
- 1 - B 04 AND2 s 3 0 0 1 reset~23
- 5 - B 04 AND2 s 3 0 0 1 reset~24
- 7 - A 21 AND2 s 3 0 0 1 reset~25
- 6 - C 17 AND2 s 3 0 0 1 reset~26
- 4 - A 17 AND2 s 3 0 0 1 reset~27
- 4 - C 05 DFFE + 1 2 1 0 Q03 (:90)
- 5 - A 17 DFFE + 1 2 1 0 Q02 (:91)
- 1 - C 17 DFFE + 1 2 1 0 Q01 (:92)
- 2 - A 21 DFFE + 1 2 1 0 Q00 (:93)
- 7 - B 04 DFFE + 1 2 1 0 Q13 (:94)
- 4 - B 04 DFFE + 1 2 1 0 Q12 (:95)
- 1 - A 13 DFFE + 1 2 1 0 Q11 (:96)
- 5 - A 13 DFFE + 1 2 1 0 Q10 (:97)
- 6 - A 13 DFFE + 1 2 1 0 Q23 (:98)
- 2 - B 02 DFFE + 1 2 1 0 Q22 (:99)
- 3 - B 02 DFFE + 1 2 1 0 Q21 (:100)
- 2 - B 04 DFFE + 1 2 1 0 Q20 (:101)
- 7 - C 05 DFFE + 1 2 1 0 Q33 (:102)
- 1 - C 05 DFFE + 1 2 1 0 Q32 (:103)
- 8 - A 17 DFFE + 1 2 1 0 Q31 (:104)
- 6 - A 17 DFFE + 1 2 1 0 Q30 (:105)
- 1 - B 07 DFFE + 1 2 1 0 Q43 (:106)
- 8 - C 17 DFFE + 1 2 1 0 Q42 (:107)
- 2 - C 17 DFFE + 1 2 1 0 Q41 (:108)
- 1 - A 21 DFFE + 1 2 1 0 Q40 (:109)
- 3 - A 21 DFFE + 1 2 1 0 Q53 (:110)
- 2 - B 07 DFFE + 1 2 1 0 Q52 (:111)
- 8 - B 07 DFFE + 1 2 1 0 Q51 (:112)
- 3 - A 15 DFFE + 1 2 1 0 Q50 (:113)
- 1 - A 15 DFFE + 1 2 1 0 Q63 (:114)
- 7 - A 15 DFFE + 1 2 1 0 Q62 (:115)
- 4 - B 09 DFFE + 1 2 1 0 Q61 (:116)
- 8 - B 09 DFFE + 1 2 1 0 Q60 (:117)
- 2 - B 09 AND2 s 2 0 0 28 ~216~1
- 8 - C 05 OR2 s 2 2 0 1 ~838~1
- 7 - A 17 OR2 s 2 2 0 1 ~844~1
- 7 - C 17 OR2 s 2 2 0 1 ~850~1
- 8 - A 21 OR2 s 2 2 0 1 ~856~1
- 6 - B 04 OR2 s 2 2 0 1 ~862~1
- 3 - B 04 OR2 s 2 2 0 1 ~868~1
- 8 - A 13 OR2 s 2 2 0 1 ~874~1
- 7 - A 13 OR2 s 2 2 0 1 ~880~1
- 3 - A 13 OR2 s 2 2 0 1 ~886~1
- 8 - B 02 OR2 s 2 2 0 1 ~892~1
- 6 - B 02 OR2 s 2 2 0 1 ~898~1
- 1 - B 02 OR2 s 2 2 0 1 ~904~1
- 5 - C 05 OR2 s 2 2 0 1 ~910~1
- 3 - C 05 OR2 s 2 2 0 1 ~916~1
- 3 - A 17 OR2 s 2 2 0 1 ~922~1
- 2 - A 17 OR2 s 2 2 0 1 ~928~1
- 7 - B 07 OR2 s 2 2 0 1 ~934~1
- 5 - C 17 OR2 s 2 2 0 1 ~940~1
- 4 - C 17 OR2 s 2 2 0 1 ~946~1
- 6 - A 21 OR2 s 2 2 0 1 ~952~1
- 5 - A 21 OR2 s 2 2 0 1 ~958~1
- 5 - B 07 OR2 s 2 2 0 1 ~964~1
- 4 - B 07 OR2 s 2 2 0 1 ~970~1
- 8 - A 15 OR2 s 2 2 0 1 ~976~1
- 5 - A 15 OR2 s 2 2 0 1 ~982~1
- 4 - A 15 OR2 s 2 2 0 1 ~988~1
- 7 - B 09 OR2 s 2 2 0 1 ~994~1
- 1 - B 09 OR2 s 3 0 0 28 ~1000~1
- 5 - B 09 OR2 s 2 2 0 1 ~1000~2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\clock\fenlu.rpt
fenlu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 17/ 96( 17%) 0/ 48( 0%) 20/ 48( 41%) 8/16( 50%) 4/16( 25%) 0/16( 0%)
B: 11/ 96( 11%) 16/ 48( 33%) 0/ 48( 0%) 6/16( 37%) 5/16( 31%) 0/16( 0%)
C: 11/ 96( 11%) 4/ 48( 8%) 4/ 48( 8%) 6/16( 37%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
02: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
06: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
11: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
15: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
16: 5/24( 20%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
18: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
19: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
22: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
23: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\clock\fenlu.rpt
fenlu
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 28 clk
Device-Specific Information: c:\clock\fenlu.rpt
fenlu
** EQUATIONS **
b00 : INPUT;
b01 : INPUT;
b02 : INPUT;
b03 : INPUT;
b10 : INPUT;
b11 : INPUT;
b12 : INPUT;
b13 : INPUT;
b20 : INPUT;
b21 : INPUT;
b22 : INPUT;
b23 : INPUT;
b30 : INPUT;
b31 : INPUT;
b32 : INPUT;
b33 : INPUT;
b40 : INPUT;
b41 : INPUT;
b42 : INPUT;
b43 : INPUT;
b50 : INPUT;
b51 : INPUT;
b52 : INPUT;
b53 : INPUT;
b60 : INPUT;
b61 : INPUT;
b62 : INPUT;
b63 : INPUT;
clk : INPUT;
c00 : INPUT;
c01 : INPUT;
c02 : INPUT;
c03 : INPUT;
c10 : INPUT;
c11 : INPUT;
c12 : INPUT;
c13 : INPUT;
c20 : INPUT;
c21 : INPUT;
c22 : INPUT;
c23 : INPUT;
c30 : INPUT;
c31 : INPUT;
c32 : INPUT;
c33 : INPUT;
c40 : INPUT;
c41 : INPUT;
c42 : INPUT;
c43 : INPUT;
c50 : INPUT;
c51 : INPUT;
c52 : INPUT;
c53 : INPUT;
c60 : INPUT;
c61 : INPUT;
c62 : INPUT;
c63 : INPUT;
en0 : INPUT;
en1 : INPUT;
reset : INPUT;
set : INPUT;
-- Node name is 'b03~1'
-- Equation name is 'b03~1', location is LC6_C5, type is buried.
-- synthesized logic cell
_LC6_C5 = LCELL( _EQ001);
_EQ001 = b03 & !en0 & !en1;
-- Node name is 'd00'
-- Equation name is 'd00', type is output
d00 = Q00;
-- Node name is 'd01'
-- Equation name is 'd01', type is output
d01 = Q01;
-- Node name is 'd02'
-- Equation name is 'd02', type is output
d02 = Q02;
-- Node name is 'd03'
-- Equation name is 'd03', type is output
d03 = Q03;
-- Node name is 'd10'
-- Equation name is 'd10', type is output
d10 = Q10;
-- Node name is 'd11'
-- Equation name is 'd11', type is output
d11 = Q11;
-- Node name is 'd12'
-- Equation name is 'd12', type is output
d12 = Q12;
-- Node name is 'd13'
-- Equation name is 'd13', type is output
d13 = Q13;
-- Node name is 'd20'
-- Equation name is 'd20', type is output
d20 = Q20;
-- Node name is 'd21'
-- Equation name is 'd21', type is output
d21 = Q21;
-- Node name is 'd22'
-- Equation name is 'd22', type is output
d22 = Q22;
-- Node name is 'd23'
-- Equation name is 'd23', type is output
d23 = Q23;
-- Node name is 'd30'
-- Equation name is 'd30', type is output
d30 = Q30;
-- Node name is 'd31'
-- Equation name is 'd31', type is output
d31 = Q31;
-- Node name is 'd32'
-- Equation name is 'd32', type is output
d32 = Q32;
-- Node name is 'd33'
-- Equation name is 'd33', type is output
d33 = Q33;
-- Node name is 'd40'
-- Equation name is 'd40', type is output
d40 = Q40;
-- Node name is 'd41'
-- Equation name is 'd41', type is output
d41 = Q41;
-- Node name is 'd42'
-- Equation name is 'd42', type is output
d42 = Q42;
-- Node name is 'd43'
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