📄 fenlu.rpt
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Project Information c:\clock\fenlu.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 06/29/2007 23:52:35
Copyright (C) 1988-2002 Altera Corporation
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support information, device programming or simulation file, and any other
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use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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the intellectual property, including patents, copyrights, trademarks,
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***** Project compilation was successful
FENLU
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
fenlu EP1K10TC144-1 61 28 0 0 0 % 86 14 %
User Pins: 61 28 0
Device-Specific Information: c:\clock\fenlu.rpt
fenlu
***** Logic for device 'fenlu' compiled without errors.
Device: EP1K10TC144-1
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Enable Lock Output = OFF
Device-Specific Information: c:\clock\fenlu.rpt
fenlu
** ERROR SUMMARY **
Info: Chip 'fenlu' in device 'EP1K10TC144-1' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R R R
E E E
V S S S
V C r E E E V
C C e R R R C
b b c d d G c b b c C d b c c G b I s c s G V d V b V c c C b c d b d c
4 5 4 4 0 N 5 6 3 1 I 3 3 3 0 N 5 N e 6 e N E 6 E 5 E 2 2 I 1 1 2 6 2 6
1 3 0 0 0 D 0 3 3 0 O 0 1 1 2 D 0 T t 0 t D D 0 D 1 D 1 2 O 2 3 0 1 1 1
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | N.C.
N.C. | 6 103 | VCCINT
d63 | 7 102 | c00
b02 | 8 101 | N.C.
d50 | 9 100 | b23
N.C. | 10 99 | N.C.
d10 | 11 98 | b62
N.C. | 12 97 | b00
c53 | 13 96 | b42
d31 | 14 95 | c23
GND | 15 94 | VCCIO
VCCINT | 16 93 | GND
b60 | 17 92 | d43
c20 | 18 91 | d52
c51 | 19 EP1K10TC144-1 90 | d12
N.C. | 20 89 | N.C.
b43 | 21 88 | b13
N.C. | 22 87 | d13
b20 | 23 86 | d51
VCCIO | 24 85 | VCCINT
GND | 25 84 | GND
d01 | 26 83 | b03
d41 | 27 82 | N.C.
N.C. | 28 81 | b01
c32 | 29 80 | d03
c01 | 30 79 | c42
N.C. | 31 78 | d33
c41 | 32 77 | ^MSEL0
d42 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
b30 | 36 73 | d22
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
b b d G b c c d V b d c d V d G V e c e G G c c V b c c d G c b b d V c
4 1 5 N 5 6 3 0 C 1 6 1 1 C 2 N C n l n N N 4 0 C 2 1 5 6 N 6 3 2 3 C 3
0 0 3 D 2 3 0 2 C 1 2 1 1 C 3 D C 0 k 1 D D 3 3 C 2 2 2 1 D 2 2 1 2 C 3
I I _ _ I I
O N C C O O
T K K
L L
K K
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: c:\clock\fenlu.rpt
fenlu
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A13 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 12/22( 54%)
A15 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
A16 7/ 8( 87%) 3/ 8( 37%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
A17 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 12/22( 54%)
A21 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 12/22( 54%)
B2 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 12/22( 54%)
B4 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 11/22( 50%)
B7 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
B9 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
C5 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
C17 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 12/22( 54%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 83/86 ( 96%)
Total logic cells used: 86/576 ( 14%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.63/4 ( 90%)
Total fan-in: 313/2304 ( 13%)
Total input pins required: 61
Total input I/O cell registers required: 0
Total output pins required: 28
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 86
Total flipflops required: 28
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 58/ 576 ( 10%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8 7 8 0 0 0 8 0 0 0 39/0
B: 0 8 0 7 0 0 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31/0
C: 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 16/0
Total: 0 8 0 7 8 0 8 0 8 0 0 0 0 8 0 8 7 16 0 0 0 8 0 0 0 86/0
Device-Specific Information: c:\clock\fenlu.rpt
fenlu
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
97 - - A -- INPUT ^ 0 0 0 1 b00
81 - - C -- INPUT ^ 0 0 0 1 b01
8 - - A -- INPUT ^ 0 0 0 1 b02
83 - - C -- INPUT ^ 0 0 0 1 b03
38 - - - 22 INPUT ^ 0 0 0 1 b10
46 - - - 17 INPUT ^ 0 0 0 1 b11
114 - - - 04 INPUT ^ 0 0 0 1 b12
88 - - B -- INPUT ^ 0 0 0 1 b13
23 - - B -- INPUT ^ 0 0 0 1 b20
69 - - - 06 INPUT ^ 0 0 0 1 b21
62 - - - 11 INPUT ^ 0 0 0 1 b22
100 - - A -- INPUT ^ 0 0 0 1 b23
36 - - - 24 INPUT ^ 0 0 0 1 b30
132 - - - 16 INPUT ^ 0 0 0 1 b31
68 - - - 07 INPUT ^ 0 0 0 1 b32
136 - - - 19 INPUT ^ 0 0 0 1 b33
37 - - - 23 INPUT ^ 0 0 0 1 b40
144 - - - 24 INPUT ^ 0 0 0 1 b41
96 - - A -- INPUT ^ 0 0 0 1 b42
21 - - B -- INPUT ^ 0 0 0 1 b43
128 - - - 13 INPUT ^ 0 0 0 1 b50
119 - - - 08 INPUT ^ 0 0 0 1 b51
41 - - - 20 INPUT ^ 0 0 0 1 b52
143 - - - 24 INPUT ^ 0 0 0 1 b53
17 - - B -- INPUT ^ 0 0 0 1 b60
111 - - - 02 INPUT ^ 0 0 0 1 b61
98 - - A -- INPUT ^ 0 0 0 1 b62
137 - - - 19 INPUT ^ 0 0 0 1 b63
55 - - - -- INPUT G ^ 0 0 0 0 clk
102 - - A -- INPUT ^ 0 0 0 1 c00
30 - - C -- INPUT ^ 0 0 0 1 c01
130 - - - 14 INPUT ^ 0 0 0 1 c02
60 - - - 12 INPUT ^ 0 0 0 1 c03
135 - - - 18 INPUT ^ 0 0 0 1 c10
48 - - - 15 INPUT ^ 0 0 0 1 c11
63 - - - 11 INPUT ^ 0 0 0 1 c12
113 - - - 03 INPUT ^ 0 0 0 1 c13
18 - - B -- INPUT ^ 0 0 0 1 c20
117 - - - 06 INPUT ^ 0 0 0 1 c21
116 - - - 05 INPUT ^ 0 0 0 1 c22
95 - - A -- INPUT ^ 0 0 0 1 c23
43 - - - 18 INPUT ^ 0 0 0 1 c30
131 - - - 15 INPUT ^ 0 0 0 1 c31
29 - - C -- INPUT ^ 0 0 0 1 c32
72 - - - 04 INPUT ^ 0 0 0 1 c33
142 - - - 23 INPUT ^ 0 0 0 1 c40
32 - - C -- INPUT ^ 0 0 0 1 c41
79 - - C -- INPUT ^ 0 0 0 1 c42
59 - - - 12 INPUT ^ 0 0 0 1 c43
138 - - - 20 INPUT ^ 0 0 0 1 c50
19 - - B -- INPUT ^ 0 0 0 1 c51
64 - - - 10 INPUT ^ 0 0 0 1 c52
13 - - A -- INPUT ^ 0 0 0 1 c53
125 - - - -- INPUT ^ 0 0 0 1 c60
109 - - - 01 INPUT ^ 0 0 0 1 c61
67 - - - 08 INPUT ^ 0 0 0 1 c62
42 - - - 19 INPUT ^ 0 0 0 1 c63
54 - - - -- INPUT ^ 0 0 0 30 en0
56 - - - -- INPUT ^ 0 0 0 30 en1
126 - - - -- INPUT ^ 0 0 0 28 reset
124 - - - -- INPUT ^ 0 0 0 29 set
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\clock\fenlu.rpt
fenlu
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
140 - - - 21 OUTPUT 0 1 0 0 d00
26 - - C -- OUTPUT 0 1 0 0 d01
44 - - - 18 OUTPUT 0 1 0 0 d02
80 - - C -- OUTPUT 0 1 0 0 d03
11 - - A -- OUTPUT 0 1 0 0 d10
49 - - - 14 OUTPUT 0 1 0 0 d11
90 - - B -- OUTPUT 0 1 0 0 d12
87 - - B -- OUTPUT 0 1 0 0 d13
112 - - - 03 OUTPUT 0 1 0 0 d20
110 - - - 01 OUTPUT 0 1 0 0 d21
73 - - - 02 OUTPUT 0 1 0 0 d22
51 - - - 13 OUTPUT 0 1 0 0 d23
133 - - - 17 OUTPUT 0 1 0 0 d30
14 - - A -- OUTPUT 0 1 0 0 d31
70 - - - 05 OUTPUT 0 1 0 0 d32
78 - - C -- OUTPUT 0 1 0 0 d33
141 - - - 22 OUTPUT 0 1 0 0 d40
27 - - C -- OUTPUT 0 1 0 0 d41
33 - - C -- OUTPUT 0 1 0 0 d42
92 - - B -- OUTPUT 0 1 0 0 d43
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