📄 uart_top.fit.rpt
字号:
; 2 ; 1 ; 80 ; 0 / 80 ( 0 % ) ; 1 / 160 ( < 1 % ) ;
; 2 ; 2 ; 80 ; 0 / 80 ( 0 % ) ; 1 / 160 ( < 1 % ) ;
; 2 ; 3 ; 80 ; 0 / 80 ( 0 % ) ; 0 / 160 ( 0 % ) ;
; 2 ; 4 ; 80 ; 0 / 80 ( 0 % ) ; 3 / 160 ( 2 % ) ;
; 2 ; 5 ; 80 ; 0 / 80 ( 0 % ) ; 3 / 160 ( 2 % ) ;
; 2 ; 6 ; 80 ; 0 / 80 ( 0 % ) ; 3 / 160 ( 2 % ) ;
; 2 ; 7 ; 80 ; 0 / 80 ( 0 % ) ; 2 / 160 ( 1 % ) ;
; 2 ; 8 ; 80 ; 0 / 80 ( 0 % ) ; 3 / 160 ( 2 % ) ;
; 2 ; 9 ; 80 ; 0 / 80 ( 0 % ) ; 2 / 160 ( 1 % ) ;
; 2 ; 10 ; 80 ; 0 / 80 ( 0 % ) ; 2 / 160 ( 1 % ) ;
; 2 ; 11 ; 80 ; 0 / 80 ( 0 % ) ; 0 / 160 ( 0 % ) ;
; Total ; ; 1760 ; 0 / 1760 ( 0 % ) ; 21 / 3520 ( < 1 % ) ;
+--------------+------+------------------------+-------------------+------------------------+
+-----------------------------------------------------------------------------+
; ESB Column Interconnect ;
+-------+------------------------+-------------------+------------------------+
; Col. ; Interconnect Available ; Interconnect Used ; Half Interconnect Used ;
+-------+------------------------+-------------------+------------------------+
; 0 ; 128 ; 0 / 128 ( 0 % ) ; 0 / 256 ( 0 % ) ;
; 1 ; 128 ; 0 / 128 ( 0 % ) ; 0 / 256 ( 0 % ) ;
; Total ; 256 ; 0 / 256 ( 0 % ) ; 0 / 512 ( 0 % ) ;
+-------+------------------------+-------------------+------------------------+
+------------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+-----------------------------------+------------------------------------+
; Resource ; Usage ;
+-----------------------------------+------------------------------------+
; Registers ; 63 / 1,200 ( 5 % ) ;
; Logic elements in carry chains ; 8 ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 36 / 92 ( 39 % ) ;
; -- Clock pins ; 4 / 4 ( 100 % ) ;
; -- Dedicated input pins ; 1 / 4 ( 25 % ) ;
; Global signals ; 5 ;
; ESBs ; 0 / 12 ( 0 % ) ;
; Macrocells ; 0 / 192 ( 0 % ) ;
; ESB pterm bits used ; 0 / 24,576 ( 0 % ) ;
; ESB CAM bits used ; 0 / 24,576 ( 0 % ) ;
; Total memory bits ; 0 / 24,576 ( 0 % ) ;
; Total RAM block bits ; 0 / 24,576 ( 0 % ) ;
; FastRow interconnects ; 0 / 120 ( 0 % ) ;
; Maximum fan-out node ; rest ;
; Maximum fan-out ; 42 ;
; Highest non-global fan-out signal ; uart_emitter:uart_emitter_a|serial ;
; Highest non-global fan-out ; 11 ;
; Total fan-out ; 347 ;
; Average fan-out ; 2.87 ;
+-----------------------------------+------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+-----------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+-----------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------+
; |uart_top ; 85 (5) ; 63 ; 0 ; 36 ; 0 ; 22 (5) ; 33 (0) ; 30 (0) ; 8 (0) ; 0 (0) ; |uart_top ;
; |uart_clk:uart_clk_gen_a| ; 20 (0) ; 15 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 15 (0) ; 8 (0) ; 0 (0) ; |uart_top|uart_clk:uart_clk_gen_a ;
; |divide_by_13:divide_13| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_13:divide_13 ;
; |divide_by_256:divide_256| ; 16 (16) ; 11 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 11 (11) ; 8 (8) ; 0 (0) ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256 ;
; |uart_emitter:uart_emitter_a| ; 28 (28) ; 22 ; 0 ; 0 ; 0 ; 6 (6) ; 18 (18) ; 4 (4) ; 0 (0) ; 0 (0) ; |uart_top|uart_emitter:uart_emitter_a ;
; |uart_receive:uart_receiver_a| ; 32 (32) ; 26 ; 0 ; 0 ; 0 ; 6 (6) ; 15 (15) ; 11 (11) ; 0 (0) ; 0 (0) ; |uart_top|uart_receive:uart_receiver_a ;
+-----------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------------------------------------------------+
; Delay Chain Summary ;
+------------------+----------+-------------+-----------------------+-------------------------+---------------------+-----+
; Name ; Pin Type ; Pad to Core ; Pad to Input Register ; Core to Output Register ; Core to CE Register ; TCO ;
+------------------+----------+-------------+-----------------------+-------------------------+---------------------+-----+
; sel_baud_rate[0] ; Input ; ON ; OFF ; OFF ; OFF ; OFF ;
; sel_baud_rate[1] ; Input ; ON ; OFF ; OFF ; OFF ; OFF ;
; sel_baud_rate[2] ; Input ; ON ; OFF ; OFF ; OFF ; OFF ;
; rest ; Input ; OFF ; OFF ; OFF ; OFF ; OFF ;
; load_bus_reg ; Input ; ON ; OFF ; OFF ; OFF ; OFF ;
; date_bus[0] ; Input ; ON ; OFF ; OFF ; OFF ; OFF ;
; date_bus[2] ; Input ; ON ; OFF ; OFF ; OFF ; OFF ;
; date_bus[4] ; Input ; ON ; OFF ; OFF ; OFF ; OFF ;
; date_bus[7] ; Input ; ON ; OFF ; OFF ; OFF ; OFF ;
; sys_clock ; Input ; OFF ; OFF ; OFF ; OFF ; OFF ;
; date_bus[6] ; Input ; ON ; OFF ; OFF ; OFF ; OFF ;
; date_bus[3] ; Input ; ON ; OFF ; OFF ; OFF ; OFF ;
; date_bus[5] ; Input ; ON ; OFF ; OFF ; OFF ; OFF ;
; date_bus[1] ; Input ; ON ; OFF ; OFF ; OFF ; OFF ;
; finish_F ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; bit_counter[0] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; bit_counter[1] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; bit_counter[2] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; bit_counter[3] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; counter[0] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; counter[1] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; counter[2] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; counter[3] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; bus[0] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; bus[1] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; bus[2] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; bus[3] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; bus[4] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; bus[5] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; bus[6] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; bus[7] ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; error ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; finish_s ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; serial ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; clock ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
; sample_clock ; Output ; OFF ; OFF ; OFF ; OFF ; OFF ;
+------------------+----------+-------------+-----------------------+-------------------------+---------------------+-----+
+-----------------------------+
; I/O Bank Usage ;
+----------+------------------+
; I/O Bank ; Usage ;
+----------+------------------+
; 1 ; 0 / 15 ( 0 % ) ;
; 2 ; 3 / 13 ( 23 % ) ;
; 3 ; 8 / 11 ( 73 % ) ;
; 4 ; 10 / 12 ( 83 % ) ;
; 5 ; 6 / 14 ( 43 % ) ;
; 6 ; 0 / 12 ( 0 % ) ;
; 7 ; 6 / 6 ( 100 % ) ;
; 8 ; 3 / 9 ( 33 % ) ;
+----------+------------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/verilog/uart/uart_top.pin.
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Tue Dec 12 00:57:28 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off uart_top -c uart_top
Info: Automatically selected device EP20K30ETC144-1 for design uart_top
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Promoted cell "sys_clock" to global signal automatically
Info: Promoted cell "uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34" to global signal automatically
Info: Promoted cell "uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2]" to global signal automatically
Info: Promoted cell "uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3]" to global signal automatically
Info: Promoted cell "rest" to global signal automatically
Info: Started fitting attempt 1 on Tue Dec 12 2006 at 00:57:37
Warning: Performance of this circuit may degrade because the Fitter Delay Information is not loaded.
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Design requires the following device routing resources:
Info: Overall column FastTrack interconnect = 1%
Info: Overall row FastTrack interconnect = 1%
Info: Maximum column FastTrack interconnect = 2%
Info: Maximum row FastTrack interconnect = 4%
Info: Estimated most critical path is register to register delay of 2.649 ns
Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LAB_7_E2; Fanout = 11; REG Node = 'uart_emitter:uart_emitter_a|serial'
Info: 2: + IC(0.843 ns) + CELL(0.890 ns) = 1.894 ns; Loc. = LAB_5_E2; Fanout = 8; COMB Node = 'uart_receive:uart_receiver_a|bus[0]~15'
Info: 3: + IC(0.246 ns) + CELL(0.509 ns) = 2.649 ns; Loc. = LAB_4_E2; Fanout = 1; REG Node = 'uart_receive:uart_receiver_a|bus[0]'
Info: Total cell delay = 1.560 ns ( 58.89 % )
Info: Total interconnect delay = 1.089 ns ( 41.11 % )
Info: Fitter placement operations ending: elapsed time is 00:00:05
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:02
Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Processing ended: Tue Dec 12 00:57:47 2006
Info: Elapsed time: 00:00:21
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