uart_emitter.tan.rpt

Uart port 是一段不错的

; N/A   ; None         ; 5.146 ns   ; load_bus_reg ; bus_reg[7] ; clock    ;
; N/A   ; None         ; 5.146 ns   ; load_bus_reg ; bus_reg[6] ; clock    ;
; N/A   ; None         ; 5.146 ns   ; load_bus_reg ; bus_reg[3] ; clock    ;
; N/A   ; None         ; 5.146 ns   ; load_bus_reg ; bus_reg[1] ; clock    ;
; N/A   ; None         ; 4.105 ns   ; load_bus_reg ; state.idle ; clock    ;
; N/A   ; None         ; 3.670 ns   ; bus[5]       ; bus_reg[5] ; clock    ;
; N/A   ; None         ; 3.598 ns   ; load_bus_reg ; state.bit0 ; clock    ;
; N/A   ; None         ; 3.454 ns   ; bus[1]       ; bus_reg[1] ; clock    ;
; N/A   ; None         ; 3.453 ns   ; bus[6]       ; bus_reg[6] ; clock    ;
; N/A   ; None         ; 3.441 ns   ; bus[3]       ; bus_reg[3] ; clock    ;
; N/A   ; None         ; 3.428 ns   ; bus[2]       ; bus_reg[2] ; clock    ;
; N/A   ; None         ; 3.344 ns   ; bus[0]       ; bus_reg[0] ; clock    ;
; N/A   ; None         ; 3.067 ns   ; rest         ; bus_reg[5] ; clock    ;
; N/A   ; None         ; 3.014 ns   ; rest         ; bus_reg[0] ; clock    ;
; N/A   ; None         ; 3.013 ns   ; rest         ; bus_reg[2] ; clock    ;
; N/A   ; None         ; 2.954 ns   ; bus[4]       ; bus_reg[4] ; clock    ;
; N/A   ; None         ; 2.940 ns   ; bus[7]       ; bus_reg[7] ; clock    ;
; N/A   ; None         ; 2.290 ns   ; rest         ; bus_reg[4] ; clock    ;
; N/A   ; None         ; 2.290 ns   ; rest         ; bus_reg[7] ; clock    ;
; N/A   ; None         ; 2.290 ns   ; rest         ; bus_reg[6] ; clock    ;
; N/A   ; None         ; 2.290 ns   ; rest         ; bus_reg[3] ; clock    ;
; N/A   ; None         ; 2.290 ns   ; rest         ; bus_reg[1] ; clock    ;
+-------+--------------+------------+--------------+------------+----------+


+---------------------------------------------------------------------------+
; tco                                                                       ;
+-------+--------------+------------+---------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From          ; To       ; From Clock ;
+-------+--------------+------------+---------------+----------+------------+
; N/A   ; None         ; 6.203 ns   ; finish_F~reg0 ; finish_F ; clock      ;
; N/A   ; None         ; 5.536 ns   ; serial~reg0   ; serial   ; clock      ;
+-------+--------------+------------+---------------+----------+------------+


+--------------------------------------------------------------------------------+
; th                                                                             ;
+---------------+-------------+-----------+--------------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From         ; To         ; To Clock ;
+---------------+-------------+-----------+--------------+------------+----------+
; N/A           ; None        ; -1.728 ns ; rest         ; bus_reg[4] ; clock    ;
; N/A           ; None        ; -1.728 ns ; rest         ; bus_reg[7] ; clock    ;
; N/A           ; None        ; -1.728 ns ; rest         ; bus_reg[6] ; clock    ;
; N/A           ; None        ; -1.728 ns ; rest         ; bus_reg[3] ; clock    ;
; N/A           ; None        ; -1.728 ns ; rest         ; bus_reg[1] ; clock    ;
; N/A           ; None        ; -2.378 ns ; bus[7]       ; bus_reg[7] ; clock    ;
; N/A           ; None        ; -2.392 ns ; bus[4]       ; bus_reg[4] ; clock    ;
; N/A           ; None        ; -2.451 ns ; rest         ; bus_reg[2] ; clock    ;
; N/A           ; None        ; -2.452 ns ; rest         ; bus_reg[0] ; clock    ;
; N/A           ; None        ; -2.505 ns ; rest         ; bus_reg[5] ; clock    ;
; N/A           ; None        ; -2.782 ns ; bus[0]       ; bus_reg[0] ; clock    ;
; N/A           ; None        ; -2.866 ns ; bus[2]       ; bus_reg[2] ; clock    ;
; N/A           ; None        ; -2.879 ns ; bus[3]       ; bus_reg[3] ; clock    ;
; N/A           ; None        ; -2.891 ns ; bus[6]       ; bus_reg[6] ; clock    ;
; N/A           ; None        ; -2.892 ns ; bus[1]       ; bus_reg[1] ; clock    ;
; N/A           ; None        ; -3.036 ns ; load_bus_reg ; state.bit0 ; clock    ;
; N/A           ; None        ; -3.108 ns ; bus[5]       ; bus_reg[5] ; clock    ;
; N/A           ; None        ; -3.543 ns ; load_bus_reg ; state.idle ; clock    ;
; N/A           ; None        ; -4.584 ns ; load_bus_reg ; bus_reg[4] ; clock    ;
; N/A           ; None        ; -4.584 ns ; load_bus_reg ; bus_reg[7] ; clock    ;
; N/A           ; None        ; -4.584 ns ; load_bus_reg ; bus_reg[6] ; clock    ;
; N/A           ; None        ; -4.584 ns ; load_bus_reg ; bus_reg[3] ; clock    ;
; N/A           ; None        ; -4.584 ns ; load_bus_reg ; bus_reg[1] ; clock    ;
; N/A           ; None        ; -5.307 ns ; load_bus_reg ; bus_reg[2] ; clock    ;
; N/A           ; None        ; -5.308 ns ; load_bus_reg ; bus_reg[0] ; clock    ;
; N/A           ; None        ; -5.361 ns ; load_bus_reg ; bus_reg[5] ; clock    ;
+---------------+-------------+-----------+--------------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Mon Dec 11 21:41:05 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off uart_emitter -c uart_emitter
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 290.02 MHz between source register "state.bit4" and destination register "serial~reg0"
    Info: fmax restricted to clock pin edge rate 3.448 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.700 ns
            Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC1_3_C2; Fanout = 2; REG Node = 'state.bit4'
            Info: 2: + IC(0.967 ns) + CELL(0.694 ns) = 1.822 ns; Loc. = LC5_2_C2; Fanout = 1; COMB Node = 'Select~148'
            Info: 3: + IC(0.000 ns) + CELL(0.532 ns) = 2.354 ns; Loc. = LC6_2_C2; Fanout = 1; COMB Node = 'Select~146'
            Info: 4: + IC(0.267 ns) + CELL(0.079 ns) = 2.700 ns; Loc. = LC8_1_C2; Fanout = 2; REG Node = 'serial~reg0'
            Info: Total cell delay = 1.466 ns ( 54.30 % )
            Info: Total interconnect delay = 1.234 ns ( 45.70 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clock" to destination register is 1.663 ns
                Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 22; CLK Node = 'clock'
                Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC8_1_C2; Fanout = 2; REG Node = 'serial~reg0'
                Info: Total cell delay = 0.890 ns ( 53.52 % )
                Info: Total interconnect delay = 0.773 ns ( 46.48 % )
            Info: - Longest clock path from clock "clock" to source register is 1.663 ns
                Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 22; CLK Node = 'clock'
                Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC1_3_C2; Fanout = 2; REG Node = 'state.bit4'
                Info: Total cell delay = 0.890 ns ( 53.52 % )
                Info: Total interconnect delay = 0.773 ns ( 46.48 % )
        Info: + Micro clock to output delay of source is 0.335 ns
        Info: + Micro setup delay of destination is 0.198 ns
Info: tsu for register "bus_reg[5]" (data pin = "load_bus_reg", clock pin = "clock") is 5.923 ns
    Info: + Longest pin to register delay is 7.388 ns
        Info: 1: + IC(0.000 ns) + CELL(1.310 ns) = 1.310 ns; Loc. = PIN_142; Fanout = 3; PIN Node = 'load_bus_reg'
        Info: 2: + IC(3.635 ns) + CELL(0.890 ns) = 5.835 ns; Loc. = LC4_2_C2; Fanout = 8; COMB Node = 'bus_reg[7]~0'
        Info: 3: + IC(1.044 ns) + CELL(0.509 ns) = 7.388 ns; Loc. = LC5_3_C2; Fanout = 1; REG Node = 'bus_reg[5]'
        Info: Total cell delay = 2.709 ns ( 36.67 % )
        Info: Total interconnect delay = 4.679 ns ( 63.33 % )
    Info: + Micro setup delay of destination is 0.198 ns
    Info: - Shortest clock path from clock "clock" to destination register is 1.663 ns
        Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 22; CLK Node = 'clock'
        Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC5_3_C2; Fanout = 1; REG Node = 'bus_reg[5]'
        Info: Total cell delay = 0.890 ns ( 53.52 % )
        Info: Total interconnect delay = 0.773 ns ( 46.48 % )
Info: tco from clock "clock" to destination pin "finish_F" through register "finish_F~reg0" is 6.203 ns
    Info: + Longest clock path from clock "clock" to source register is 1.663 ns
        Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 22; CLK Node = 'clock'
        Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC3_4_C2; Fanout = 2; REG Node = 'finish_F~reg0'
        Info: Total cell delay = 0.890 ns ( 53.52 % )
        Info: Total interconnect delay = 0.773 ns ( 46.48 % )
    Info: + Micro clock to output delay of source is 0.335 ns
    Info: + Longest register to pin delay is 4.205 ns
        Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC3_4_C2; Fanout = 2; REG Node = 'finish_F~reg0'
        Info: 2: + IC(1.634 ns) + CELL(2.410 ns) = 4.205 ns; Loc. = PIN_33; Fanout = 0; PIN Node = 'finish_F'
        Info: Total cell delay = 2.571 ns ( 61.14 % )
        Info: Total interconnect delay = 1.634 ns ( 38.86 % )
Info: th for register "bus_reg[4]" (data pin = "rest", clock pin = "clock") is -1.728 ns
    Info: + Longest clock path from clock "clock" to destination register is 1.663 ns
        Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 22; CLK Node = 'clock'
        Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC9_2_C2; Fanout = 1; REG Node = 'bus_reg[4]'
        Info: Total cell delay = 0.890 ns ( 53.52 % )
        Info: Total interconnect delay = 0.773 ns ( 46.48 % )
    Info: + Micro hold delay of destination is 0.364 ns
    Info: - Shortest pin to register delay is 3.755 ns
        Info: 1: + IC(0.000 ns) + CELL(0.960 ns) = 0.960 ns; Loc. = PIN_127; Fanout = 15; PIN Node = 'rest'
        Info: 2: + IC(1.221 ns) + CELL(0.798 ns) = 2.979 ns; Loc. = LC4_2_C2; Fanout = 8; COMB Node = 'bus_reg[7]~0'
        Info: 3: + IC(0.267 ns) + CELL(0.509 ns) = 3.755 ns; Loc. = LC9_2_C2; Fanout = 1; REG Node = 'bus_reg[4]'
        Info: Total cell delay = 2.267 ns ( 60.37 % )
        Info: Total interconnect delay = 1.488 ns ( 39.63 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Dec 11 21:41:07 2006
    Info: Elapsed time: 00:00:03