📄 uart_emitter.tan.rpt
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Timing Analyzer report for uart_emitter
Mon Dec 11 21:41:08 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clock'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+-------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+-------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 5.923 ns ; load_bus_reg ; bus_reg[5] ; -- ; clock ; 0 ;
; Worst-case tco ; N/A ; None ; 6.203 ns ; finish_F~reg0 ; finish_F ; clock ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -1.728 ns ; rest ; bus_reg[1] ; -- ; clock ; 0 ;
; Clock Setup: 'clock' ; N/A ; None ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit4 ; serial~reg0 ; clock ; clock ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+-------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP20K30ETC144-1 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock' ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit4 ; serial~reg0 ; clock ; clock ; None ; None ; 2.700 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.idle ; bus_reg[5] ; clock ; clock ; None ; None ; 2.335 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit2 ; serial~reg0 ; clock ; clock ; None ; None ; 2.333 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.idle ; bus_reg[0] ; clock ; clock ; None ; None ; 2.282 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.idle ; bus_reg[2] ; clock ; clock ; None ; None ; 2.281 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.idle ; serial~reg0 ; clock ; clock ; None ; None ; 2.207 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; bus_reg[7] ; serial~reg0 ; clock ; clock ; None ; None ; 2.185 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.over ; serial~reg0 ; clock ; clock ; None ; None ; 2.180 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit8 ; serial~reg0 ; clock ; clock ; None ; None ; 2.174 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; bus_reg[4] ; serial~reg0 ; clock ; clock ; None ; None ; 2.107 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit9 ; serial~reg0 ; clock ; clock ; None ; None ; 2.105 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit3 ; serial~reg0 ; clock ; clock ; None ; None ; 2.098 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit1 ; serial~reg0 ; clock ; clock ; None ; None ; 2.095 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; bus_reg[0] ; serial~reg0 ; clock ; clock ; None ; None ; 2.003 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit7 ; serial~reg0 ; clock ; clock ; None ; None ; 2.000 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; bus_reg[3] ; serial~reg0 ; clock ; clock ; None ; None ; 1.907 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.idle ; finish_F~reg0 ; clock ; clock ; None ; None ; 1.721 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit6 ; serial~reg0 ; clock ; clock ; None ; None ; 1.677 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; bus_reg[1] ; serial~reg0 ; clock ; clock ; None ; None ; 1.664 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit5 ; serial~reg0 ; clock ; clock ; None ; None ; 1.663 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; serial~reg0 ; serial~reg0 ; clock ; clock ; None ; None ; 1.662 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; bus_reg[2] ; serial~reg0 ; clock ; clock ; None ; None ; 1.577 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.idle ; bus_reg[1] ; clock ; clock ; None ; None ; 1.558 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.idle ; bus_reg[3] ; clock ; clock ; None ; None ; 1.558 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.idle ; bus_reg[6] ; clock ; clock ; None ; None ; 1.558 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.idle ; bus_reg[7] ; clock ; clock ; None ; None ; 1.558 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.idle ; bus_reg[4] ; clock ; clock ; None ; None ; 1.558 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; bus_reg[6] ; serial~reg0 ; clock ; clock ; None ; None ; 1.481 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.over ; finish_F~reg0 ; clock ; clock ; None ; None ; 1.339 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit3 ; state.bit4 ; clock ; clock ; None ; None ; 1.296 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit1 ; state.bit2 ; clock ; clock ; None ; None ; 1.295 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit8 ; state.bit9 ; clock ; clock ; None ; None ; 1.276 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.over ; state.idle ; clock ; clock ; None ; None ; 1.272 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit2 ; state.bit3 ; clock ; clock ; None ; None ; 1.265 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit0 ; state.bit1 ; clock ; clock ; None ; None ; 1.234 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; bus_reg[5] ; serial~reg0 ; clock ; clock ; None ; None ; 1.146 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; finish_F~reg0 ; finish_F~reg0 ; clock ; clock ; None ; None ; 1.007 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit6 ; state.bit7 ; clock ; clock ; None ; None ; 0.983 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit7 ; state.bit8 ; clock ; clock ; None ; None ; 0.983 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.idle ; state.idle ; clock ; clock ; None ; None ; 0.983 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit5 ; state.bit6 ; clock ; clock ; None ; None ; 0.969 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit9 ; state.over ; clock ; clock ; None ; None ; 0.962 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.idle ; state.bit0 ; clock ; clock ; None ; None ; 0.955 ns ;
; N/A ; Restricted to 290.02 MHz ( period = 3.448 ns ) ; state.bit4 ; state.bit5 ; clock ; clock ; None ; None ; 0.486 ns ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+--------------+------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+--------------+------------+----------+
; N/A ; None ; 5.923 ns ; load_bus_reg ; bus_reg[5] ; clock ;
; N/A ; None ; 5.870 ns ; load_bus_reg ; bus_reg[0] ; clock ;
; N/A ; None ; 5.869 ns ; load_bus_reg ; bus_reg[2] ; clock ;
; N/A ; None ; 5.146 ns ; load_bus_reg ; bus_reg[4] ; clock ;
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