uart_clk.tan.qmsg

Uart port 是一段不错的

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sel_baud_rate\[1\] register divide_by_256:divide_256\|temp0\[2\] register divide_by_256:divide_256\|temp0\[2\] 211.19 MHz 4.735 ns Internal " "Info: Clock \"sel_baud_rate\[1\]\" has Internal fmax of 211.19 MHz between source register \"divide_by_256:divide_256\|temp0\[2\]\" and destination register \"divide_by_256:divide_256\|temp0\[2\]\" (period= 4.735 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.877 ns + Longest register register " "Info: + Longest register to register delay is 1.877 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.291 ns) 0.291 ns divide_by_256:divide_256\|temp0\[2\] 1 REG LC5_15_Z2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "" { divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.321 ns) + CELL(1.265 ns) 1.877 ns divide_by_256:divide_256\|temp0\[2\] 2 REG LC5_15_Z2 2 " "Info: 2: + IC(0.321 ns) + CELL(1.265 ns) = 1.877 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.586 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.556 ns ( 82.90 % ) " "Info: Total cell delay = 1.556 ns ( 82.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.321 ns ( 17.10 % ) " "Info: Total interconnect delay = 0.321 ns ( 17.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.877 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.877 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } { 0.000ns 0.321ns } { 0.291ns 1.265ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.085 ns - Smallest " "Info: - Smallest clock skew is -2.085 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sel_baud_rate\[1\] destination 16.170 ns + Shortest register " "Info: + Shortest clock path from clock \"sel_baud_rate\[1\]\" to destination register is 16.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.845 ns) 1.845 ns sel_baud_rate\[1\] 1 CLK PIN_131 3 " "Info: 1: + IC(0.000 ns) + CELL(1.845 ns) = 1.845 ns; Loc. = PIN_131; Fanout = 3; CLK Node = 'sel_baud_rate\[1\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "" { sel_baud_rate[1] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.744 ns) + CELL(1.602 ns) 8.191 ns divide_by_256:divide_256\|clock~33 2 COMB LC9_4_O1 1 " "Info: 2: + IC(4.744 ns) + CELL(1.602 ns) = 8.191 ns; Loc. = LC9_4_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256\|clock~33'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "6.346 ns" { sel_baud_rate[1] divide_by_256:divide_256|clock~33 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.321 ns) + CELL(1.436 ns) 9.948 ns divide_by_256:divide_256\|clock~34 3 COMB LC5_5_O1 4 " "Info: 3: + IC(0.321 ns) + CELL(1.436 ns) = 9.948 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256\|clock~34'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.757 ns" { divide_by_256:divide_256|clock~33 divide_by_256:divide_256|clock~34 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.222 ns) + CELL(0.000 ns) 16.170 ns divide_by_256:divide_256\|temp0\[2\] 4 REG LC5_15_Z2 2 " "Info: 4: + IC(6.222 ns) + CELL(0.000 ns) = 16.170 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "6.222 ns" { divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.883 ns ( 30.20 % ) " "Info: Total cell delay = 4.883 ns ( 30.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.287 ns ( 69.80 % ) " "Info: Total interconnect delay = 11.287 ns ( 69.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "16.170 ns" { sel_baud_rate[1] divide_by_256:divide_256|clock~33 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "16.170 ns" { sel_baud_rate[1] sel_baud_rate[1]~out0 divide_by_256:divide_256|clock~33 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 4.744ns 0.321ns 6.222ns } { 0.000ns 1.845ns 1.602ns 1.436ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sel_baud_rate\[1\] source 18.255 ns - Longest register " "Info: - Longest clock path from clock \"sel_baud_rate\[1\]\" to source register is 18.255 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.845 ns) 1.845 ns sel_baud_rate\[1\] 1 CLK PIN_131 3 " "Info: 1: + IC(0.000 ns) + CELL(1.845 ns) = 1.845 ns; Loc. = PIN_131; Fanout = 3; CLK Node = 'sel_baud_rate\[1\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "" { sel_baud_rate[1] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.742 ns) + CELL(1.602 ns) 8.189 ns divide_by_256:divide_256\|clock~30 2 COMB LC10_4_O1 1 " "Info: 2: + IC(4.742 ns) + CELL(1.602 ns) = 8.189 ns; Loc. = LC10_4_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256\|clock~30'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "6.344 ns" { sel_baud_rate[1] divide_by_256:divide_256|clock~30 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.297 ns) + CELL(1.581 ns) 11.067 ns divide_by_256:divide_256\|clock~31 3 COMB LC3_5_O1 1 " "Info: 3: + IC(1.297 ns) + CELL(1.581 ns) = 11.067 ns; Loc. = LC3_5_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256\|clock~31'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "2.878 ns" { divide_by_256:divide_256|clock~30 divide_by_256:divide_256|clock~31 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.321 ns) + CELL(0.645 ns) 12.033 ns divide_by_256:divide_256\|clock~34 4 COMB LC5_5_O1 4 " "Info: 4: + IC(0.321 ns) + CELL(0.645 ns) = 12.033 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256\|clock~34'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "0.966 ns" { divide_by_256:divide_256|clock~31 divide_by_256:divide_256|clock~34 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.222 ns) + CELL(0.000 ns) 18.255 ns divide_by_256:divide_256\|temp0\[2\] 5 REG LC5_15_Z2 2 " "Info: 5: + IC(6.222 ns) + CELL(0.000 ns) = 18.255 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "6.222 ns" { divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.673 ns ( 31.08 % ) " "Info: Total cell delay = 5.673 ns ( 31.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.582 ns ( 68.92 % ) " "Info: Total interconnect delay = 12.582 ns ( 68.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "18.255 ns" { sel_baud_rate[1] divide_by_256:divide_256|clock~30 divide_by_256:divide_256|clock~31 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "18.255 ns" { sel_baud_rate[1] sel_baud_rate[1]~out0 divide_by_256:divide_256|clock~30 divide_by_256:divide_256|clock~31 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 4.742ns 1.297ns 0.321ns 6.222ns } { 0.000ns 1.845ns 1.602ns 1.581ns 0.645ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "16.170 ns" { sel_baud_rate[1] divide_by_256:divide_256|clock~33 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "16.170 ns" { sel_baud_rate[1] sel_baud_rate[1]~out0 divide_by_256:divide_256|clock~33 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 4.744ns 0.321ns 6.222ns } { 0.000ns 1.845ns 1.602ns 1.436ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "18.255 ns" { sel_baud_rate[1] divide_by_256:divide_256|clock~30 divide_by_256:divide_256|clock~31 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "18.255 ns" { sel_baud_rate[1] sel_baud_rate[1]~out0 divide_by_256:divide_256|clock~30 divide_by_256:divide_256|clock~31 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 4.742ns 1.297ns 0.321ns 6.222ns } { 0.000ns 1.845ns 1.602ns 1.581ns 0.645ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.603 ns + " "Info: + Micro clock to output delay of source is 0.603 ns" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.170 ns + " "Info: + Micro setup delay of destination is 0.170 ns" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.877 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.877 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } { 0.000ns 0.321ns } { 0.291ns 1.265ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "16.170 ns" { sel_baud_rate[1] divide_by_256:divide_256|clock~33 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "16.170 ns" { sel_baud_rate[1] sel_baud_rate[1]~out0 divide_by_256:divide_256|clock~33 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 4.744ns 0.321ns 6.222ns } { 0.000ns 1.845ns 1.602ns 1.436ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "18.255 ns" { sel_baud_rate[1] divide_by_256:divide_256|clock~30 divide_by_256:divide_256|clock~31 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "18.255 ns" { sel_baud_rate[1] sel_baud_rate[1]~out0 divide_by_256:divide_256|clock~30 divide_by_256:divide_256|clock~31 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 4.742ns 1.297ns 0.321ns 6.222ns } { 0.000ns 1.845ns 1.602ns 1.581ns 0.645ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sel_baud_rate\[0\] register divide_by_256:divide_256\|temp0\[2\] register divide_by_256:divide_256\|temp0\[2\] 161.32 MHz 6.199 ns Internal " "Info: Clock \"sel_baud_rate\[0\]\" has Internal fmax of 161.32 MHz between source register \"divide_by_256:divide_256\|temp0\[2\]\" and destination register \"divide_by_256:divide_256\|temp0\[2\]\" (period= 6.199 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.877 ns + Longest register register " "Info: + Longest register to register delay is 1.877 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.291 ns) 0.291 ns divide_by_256:divide_256\|temp0\[2\] 1 REG LC5_15_Z2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "" { divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.321 ns) + CELL(1.265 ns) 1.877 ns divide_by_256:divide_256\|temp0\[2\] 2 REG LC5_15_Z2 2 " "Info: 2: + IC(0.321 ns) + CELL(1.265 ns) = 1.877 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.586 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.556 ns ( 82.90 % ) " "Info: Total cell delay = 1.556 ns ( 82.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.321 ns ( 17.10 % ) " "Info: Total interconnect delay = 0.321 ns ( 17.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.877 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.877 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } { 0.000ns 0.321ns } { 0.291ns 1.265ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.549 ns - Smallest " "Info: - Smallest clock skew is -3.549 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sel_baud_rate\[0\] destination 13.161 ns + Shortest register " "Info: + Shortest clock path from clock \"sel_baud_rate\[0\]\" to destination register is 13.161 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.845 ns) 1.845 ns sel_baud_rate\[0\] 1 CLK PIN_138