uart_clk.tan.qmsg

Uart port 是一段不错的

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "14 " "Warning: Found 14 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "divide_by_256:divide_256\|clock~34 " "Info: Detected gated clock \"divide_by_256:divide_256\|clock~34\" as buffer" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "divide_by_256:divide_256\|clock~34" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "divide_by_256:divide_256\|clock~33 " "Info: Detected gated clock \"divide_by_256:divide_256\|clock~33\" as buffer" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "divide_by_256:divide_256\|clock~33" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "divide_by_256:divide_256\|clock~32 " "Info: Detected gated clock \"divide_by_256:divide_256\|clock~32\" as buffer" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "divide_by_256:divide_256\|clock~32" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divide_by_256:divide_256\|temp\[0\] " "Info: Detected ripple clock \"divide_by_256:divide_256\|temp\[0\]\" as buffer" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "divide_by_256:divide_256\|temp\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divide_by_256:divide_256\|temp\[1\] " "Info: Detected ripple clock \"divide_by_256:divide_256\|temp\[1\]\" as buffer" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "divide_by_256:divide_256\|temp\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divide_by_256:divide_256\|temp\[2\] " "Info: Detected ripple clock \"divide_by_256:divide_256\|temp\[2\]\" as buffer" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "divide_by_256:divide_256\|temp\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "divide_by_256:divide_256\|clock~31 " "Info: Detected gated clock \"divide_by_256:divide_256\|clock~31\" as buffer" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "divide_by_256:divide_256\|clock~31" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divide_by_256:divide_256\|temp\[7\] " "Info: Detected ripple clock \"divide_by_256:divide_256\|temp\[7\]\" as buffer" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "divide_by_256:divide_256\|temp\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "divide_by_256:divide_256\|clock~30 " "Info: Detected gated clock \"divide_by_256:divide_256\|clock~30\" as buffer" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "divide_by_256:divide_256\|clock~30" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divide_by_256:divide_256\|temp\[3\] " "Info: Detected ripple clock \"divide_by_256:divide_256\|temp\[3\]\" as buffer" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "divide_by_256:divide_256\|temp\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divide_by_256:divide_256\|temp\[6\] " "Info: Detected ripple clock \"divide_by_256:divide_256\|temp\[6\]\" as buffer" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "divide_by_256:divide_256\|temp\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divide_by_256:divide_256\|temp\[4\] " "Info: Detected ripple clock \"divide_by_256:divide_256\|temp\[4\]\" as buffer" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "divide_by_256:divide_256\|temp\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divide_by_13:divide_13\|temp\[3\] " "Info: Detected ripple clock \"divide_by_13:divide_13\|temp\[3\]\" as buffer" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 24 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "divide_by_13:divide_13\|temp\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divide_by_256:divide_256\|temp\[5\] " "Info: Detected ripple clock \"divide_by_256:divide_256\|temp\[5\]\" as buffer" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "divide_by_256:divide_256\|temp\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sys_clock register divide_by_256:divide_256\|temp0\[2\] register divide_by_256:divide_256\|temp0\[2\] 175.72 MHz 5.691 ns Internal " "Info: Clock \"sys_clock\" has Internal fmax of 175.72 MHz between source register \"divide_by_256:divide_256\|temp0\[2\]\" and destination register \"divide_by_256:divide_256\|temp0\[2\]\" (period= 5.691 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.877 ns + Longest register register " "Info: + Longest register to register delay is 1.877 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.291 ns) 0.291 ns divide_by_256:divide_256\|temp0\[2\] 1 REG LC5_15_Z2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "" { divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.321 ns) + CELL(1.265 ns) 1.877 ns divide_by_256:divide_256\|temp0\[2\] 2 REG LC5_15_Z2 2 " "Info: 2: + IC(0.321 ns) + CELL(1.265 ns) = 1.877 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.586 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.556 ns ( 82.90 % ) " "Info: Total cell delay = 1.556 ns ( 82.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.321 ns ( 17.10 % ) " "Info: Total interconnect delay = 0.321 ns ( 17.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.877 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.877 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } { 0.000ns 0.321ns } { 0.291ns 1.265ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.041 ns - Smallest " "Info: - Smallest clock skew is -3.041 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock destination 16.516 ns + Shortest register " "Info: + Shortest clock path from clock \"sys_clock\" to destination register is 16.516 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.451 ns) 1.451 ns sys_clock 1 CLK PIN_154 4 " "Info: 1: + IC(0.000 ns) + CELL(1.451 ns) = 1.451 ns; Loc. = PIN_154; Fanout = 4; CLK Node = 'sys_clock'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "" { sys_clock } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.491 ns) + CELL(0.894 ns) 3.836 ns divide_by_13:divide_13\|temp\[3\] 2 REG LC5_16_N1 11 " "Info: 2: + IC(1.491 ns) + CELL(0.894 ns) = 3.836 ns; Loc. = LC5_16_N1; Fanout = 11; REG Node = 'divide_by_13:divide_13\|temp\[3\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "2.385 ns" { sys_clock divide_by_13:divide_13|temp[3] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.783 ns) + CELL(0.894 ns) 7.513 ns divide_by_256:divide_256\|temp\[2\] 3 REG LC3_4_O1 3 " "Info: 3: + IC(2.783 ns) + CELL(0.894 ns) = 7.513 ns; Loc. = LC3_4_O1; Fanout = 3; REG Node = 'divide_by_256:divide_256\|temp\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "3.677 ns" { divide_by_13:divide_13|temp[3] divide_by_256:divide_256|temp[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.379 ns) + CELL(0.645 ns) 8.537 ns divide_by_256:divide_256\|clock~33 4 COMB LC9_4_O1 1 " "Info: 4: + IC(0.379 ns) + CELL(0.645 ns) = 8.537 ns; Loc. = LC9_4_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256\|clock~33'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.024 ns" { divide_by_256:divide_256|temp[2] divide_by_256:divide_256|clock~33 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.321 ns) + CELL(1.436 ns) 10.294 ns divide_by_256:divide_256\|clock~34 5 COMB LC5_5_O1 4 " "Info: 5: + IC(0.321 ns) + CELL(1.436 ns) = 10.294 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256\|clock~34'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.757 ns" { divide_by_256:divide_256|clock~33 divide_by_256:divide_256|clock~34 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.222 ns) + CELL(0.000 ns) 16.516 ns divide_by_256:divide_256\|temp0\[2\] 6 REG LC5_15_Z2 2 " "Info: 6: + IC(6.222 ns) + CELL(0.000 ns) = 16.516 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "6.222 ns" { divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.320 ns ( 32.21 % ) " "Info: Total cell delay = 5.320 ns ( 32.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.196 ns ( 67.79 % ) " "Info: Total interconnect delay = 11.196 ns ( 67.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "16.516 ns" { sys_clock divide_by_13:divide_13|temp[3] divide_by_256:divide_256|temp[2] divide_by_256:divide_256|clock~33 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "16.516 ns" { sys_clock sys_clock~out0 divide_by_13:divide_13|temp[3] divide_by_256:divide_256|temp[2] divide_by_256:divide_256|clock~33 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 1.491ns 2.783ns 0.379ns 0.321ns 6.222ns } { 0.000ns 1.451ns 0.894ns 0.894ns 0.645ns 1.436ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock source 19.557 ns - Longest register " "Info: - Longest clock path from clock \"sys_clock\" to source register is 19.557 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.451 ns) 1.451 ns sys_clock 1 CLK PIN_154 4 " "Info: 1: + IC(0.000 ns) + CELL(1.451 ns) = 1.451 ns; Loc. = PIN_154; Fanout = 4; CLK Node = 'sys_clock'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "" { sys_clock } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.491 ns) + CELL(0.894 ns) 3.836 ns divide_by_13:divide_13\|temp\[3\] 2 REG LC5_16_N1 11 " "Info: 2: + IC(1.491 ns) + CELL(0.894 ns) = 3.836 ns; Loc. = LC5_16_N1; Fanout = 11; REG Node = 'divide_by_13:divide_13\|temp\[3\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "2.385 ns" { sys_clock divide_by_13:divide_13|temp[3] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.783 ns) + CELL(0.894 ns) 7.513 ns divide_by_256:divide_256\|temp\[6\] 3 REG LC7_4_O1 3 " "Info: 3: + IC(2.783 ns) + CELL(0.894 ns) = 7.513 ns; Loc. = LC7_4_O1; Fanout = 3; REG Node = 'divide_by_256:divide_256\|temp\[6\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "3.677 ns" { divide_by_13:divide_13|temp[3] divide_by_256:divide_256|temp[6] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(1.581 ns) 9.491 ns divide_by_256:divide_256\|clock~30 4 COMB LC10_4_O1 1 " "Info: 4: + IC(0.397 ns) + CELL(1.581 ns) = 9.491 ns; Loc. = LC10_4_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256\|clock~30'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.978 ns" { divide_by_256:divide_256|temp[6] divide_by_256:divide_256|clock~30 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.297 ns) + CELL(1.581 ns) 12.369 ns divide_by_256:divide_256\|clock~31 5 COMB LC3_5_O1 1 " "Info: 5: + IC(1.297 ns) + CELL(1.581 ns) = 12.369 ns; Loc. = LC3_5_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256\|clock~31'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "2.878 ns" { divide_by_256:divide_256|clock~30 divide_by_256:divide_256|clock~31 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.321 ns) + CELL(0.645 ns) 13.335 ns divide_by_256:divide_256\|clock~34 6 COMB LC5_5_O1 4 " "Info: 6: + IC(0.321 ns) + CELL(0.645 ns) = 13.335 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256\|clock~34'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "0.966 ns" { divide_by_256:divide_256|clock~31 divide_by_256:divide_256|clock~34 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.222 ns) + CELL(0.000 ns) 19.557 ns divide_by_256:divide_256\|temp0\[2\] 7 REG LC5_15_Z2 2 " "Info: 7: + IC(6.222 ns) + CELL(0.000 ns) = 19.557 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "6.222 ns" { divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.046 ns ( 36.03 % ) " "Info: Total cell delay = 7.046 ns ( 36.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.511 ns ( 63.97 % ) " "Info: Total interconnect delay = 12.511 ns ( 63.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "19.557 ns" { sys_clock divide_by_13:divide_13|temp[3] divide_by_256:divide_256|temp[6] divide_by_256:divide_256|clock~30 divide_by_256:divide_256|clock~31 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "19.557 ns" { sys_clock sys_clock~out0 divide_by_13:divide_13|temp[3] divide_by_256:divide_256|temp[6] divide_by_256:divide_256|clock~30 divide_by_256:divide_256|clock~31 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 1.491ns 2.783ns 0.397ns 1.297ns 0.321ns 6.222ns } { 0.000ns 1.451ns 0.894ns 0.894ns 1.581ns 1.581ns 0.645ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "16.516 ns" { sys_clock divide_by_13:divide_13|temp[3] divide_by_256:divide_256|temp[2] divide_by_256:divide_256|clock~33 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "16.516 ns" { sys_clock sys_clock~out0 divide_by_13:divide_13|temp[3] divide_by_256:divide_256|temp[2] divide_by_256:divide_256|clock~33 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 1.491ns 2.783ns 0.379ns 0.321ns 6.222ns } { 0.000ns 1.451ns 0.894ns 0.894ns 0.645ns 1.436ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "19.557 ns" { sys_clock divide_by_13:divide_13|temp[3] divide_by_256:divide_256|temp[6] divide_by_256:divide_256|clock~30 divide_by_256:divide_256|clock~31 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "19.557 ns" { sys_clock sys_clock~out0 divide_by_13:divide_13|temp[3] divide_by_256:divide_256|temp[6] divide_by_256:divide_256|clock~30 divide_by_256:divide_256|clock~31 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 1.491ns 2.783ns 0.397ns 1.297ns 0.321ns 6.222ns } { 0.000ns 1.451ns 0.894ns 0.894ns 1.581ns 1.581ns 0.645ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.603 ns + " "Info: + Micro clock to output delay of source is 0.603 ns" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.170 ns + " "Info: + Micro setup delay of destination is 0.170 ns" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.877 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.877 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } { 0.000ns 0.321ns } { 0.291ns 1.265ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "16.516 ns" { sys_clock divide_by_13:divide_13|temp[3] divide_by_256:divide_256|temp[2] divide_by_256:divide_256|clock~33 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "16.516 ns" { sys_clock sys_clock~out0 divide_by_13:divide_13|temp[3] divide_by_256:divide_256|temp[2] divide_by_256:divide_256|clock~33 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 1.491ns 2.783ns 0.379ns 0.321ns 6.222ns } { 0.000ns 1.451ns 0.894ns 0.894ns 0.645ns 1.436ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "19.557 ns" { sys_clock divide_by_13:divide_13|temp[3] divide_by_256:divide_256|temp[6] divide_by_256:divide_256|clock~30 divide_by_256:divide_256|clock~31 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "19.557 ns" { sys_clock sys_clock~out0 divide_by_13:divide_13|temp[3] divide_by_256:divide_256|temp[6] divide_by_256:divide_256|clock~30 divide_by_256:divide_256|clock~31 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 1.491ns 2.783ns 0.397ns 1.297ns 0.321ns 6.222ns } { 0.000ns 1.451ns 0.894ns 0.894ns 1.581ns 1.581ns 0.645ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "sel_baud_rate\[2\] register register divide_by_256:divide_256\|temp0\[2\] divide_by_256:divide_256\|temp0\[2\] 220.99 MHz Internal " "Info: Clock \"sel_baud_rate\[2\]\" Internal fmax is restricted to 220.99 MHz between source register \"divide_by_256:divide_256\|temp0\[2\]\" and destination register \"divide_by_256:divide_256\|temp0\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 4.525 ns " "Info: fmax restricted to clock pin edge rate 4.525 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.877 ns + Longest register register " "Info: + Longest register to register delay is 1.877 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.291 ns) 0.291 ns divide_by_256:divide_256\|temp0\[2\] 1 REG LC5_15_Z2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "" { divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.321 ns) + CELL(1.265 ns) 1.877 ns divide_by_256:divide_256\|temp0\[2\] 2 REG LC5_15_Z2 2 " "Info: 2: + IC(0.321 ns) + CELL(1.265 ns) = 1.877 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.586 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.556 ns ( 82.90 % ) " "Info: Total cell delay = 1.556 ns ( 82.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.321 ns ( 17.10 % ) " "Info: Total interconnect delay = 0.321 ns ( 17.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.877 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.877 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } { 0.000ns 0.321ns } { 0.291ns 1.265ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sel_baud_rate\[2\] destination 15.017 ns + Shortest register " "Info: + Shortest clock path from clock \"sel_baud_rate\[2\]\" to destination register is 15.017 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.845 ns) 1.845 ns sel_baud_rate\[2\] 1 CLK PIN_37 1 " "Info: 1: + IC(0.000 ns) + CELL(1.845 ns) = 1.845 ns; Loc. = PIN_37; Fanout = 1; CLK Node = 'sel_baud_rate\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "" { sel_baud_rate[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.369 ns) + CELL(1.581 ns) 8.795 ns divide_by_256:divide_256\|clock~34 2 COMB LC5_5_O1 4 " "Info: 2: + IC(5.369 ns) + CELL(1.581 ns) = 8.795 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256\|clock~34'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "6.950 ns" { sel_baud_rate[2] divide_by_256:divide_256|clock~34 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.222 ns) + CELL(0.000 ns) 15.017 ns divide_by_256:divide_256\|temp0\[2\] 3 REG LC5_15_Z2 2 " "Info: 3: + IC(6.222 ns) + CELL(0.000 ns) = 15.017 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "6.222 ns" { divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.426 ns ( 22.81 % ) " "Info: Total cell delay = 3.426 ns ( 22.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.591 ns ( 77.19 % ) " "Info: Total interconnect delay = 11.591 ns ( 77.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "15.017 ns" { sel_baud_rate[2] divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "15.017 ns" { sel_baud_rate[2] sel_baud_rate[2]~out0 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 5.369ns 6.222ns } { 0.000ns 1.845ns 1.581ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sel_baud_rate\[2\] source 15.017 ns - Longest register " "Info: - Longest clock path from clock \"sel_baud_rate\[2\]\" to source register is 15.017 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.845 ns) 1.845 ns sel_baud_rate\[2\] 1 CLK PIN_37 1 " "Info: 1: + IC(0.000 ns) + CELL(1.845 ns) = 1.845 ns; Loc. = PIN_37; Fanout = 1; CLK Node = 'sel_baud_rate\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "" { sel_baud_rate[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.369 ns) + CELL(1.581 ns) 8.795 ns divide_by_256:divide_256\|clock~34 2 COMB LC5_5_O1 4 " "Info: 2: + IC(5.369 ns) + CELL(1.581 ns) = 8.795 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256\|clock~34'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "6.950 ns" { sel_baud_rate[2] divide_by_256:divide_256|clock~34 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.222 ns) + CELL(0.000 ns) 15.017 ns divide_by_256:divide_256\|temp0\[2\] 3 REG LC5_15_Z2 2 " "Info: 3: + IC(6.222 ns) + CELL(0.000 ns) = 15.017 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "6.222 ns" { divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.426 ns ( 22.81 % ) " "Info: Total cell delay = 3.426 ns ( 22.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.591 ns ( 77.19 % ) " "Info: Total interconnect delay = 11.591 ns ( 77.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "15.017 ns" { sel_baud_rate[2] divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "15.017 ns" { sel_baud_rate[2] sel_baud_rate[2]~out0 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 5.369ns 6.222ns } { 0.000ns 1.845ns 1.581ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "15.017 ns" { sel_baud_rate[2] divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "15.017 ns" { sel_baud_rate[2] sel_baud_rate[2]~out0 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 5.369ns 6.222ns } { 0.000ns 1.845ns 1.581ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "15.017 ns" { sel_baud_rate[2] divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "15.017 ns" { sel_baud_rate[2] sel_baud_rate[2]~out0 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 5.369ns 6.222ns } { 0.000ns 1.845ns 1.581ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.603 ns + " "Info: + Micro clock to output delay of source is 0.603 ns" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.170 ns + " "Info: + Micro setup delay of destination is 0.170 ns" {  } { { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "1.877 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.877 ns" { divide_by_256:divide_256|temp0[2] divide_by_256:divide_256|temp0[2] } { 0.000ns 0.321ns } { 0.291ns 1.265ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "15.017 ns" { sel_baud_rate[2] divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "15.017 ns" { sel_baud_rate[2] sel_baud_rate[2]~out0 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 5.369ns 6.222ns } { 0.000ns 1.845ns 1.581ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "15.017 ns" { sel_baud_rate[2] divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "15.017 ns" { sel_baud_rate[2] sel_baud_rate[2]~out0 divide_by_256:divide_256|clock~34 divide_by_256:divide_256|temp0[2] } { 0.000ns 0.000ns 5.369ns 6.222ns } { 0.000ns 1.845ns 1.581ns 0.000ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_clk" "UNKNOWN" "V1" "F:/verilog/uart/db/uart_clk.quartus_db" { Floorplan "F:/verilog/uart/" "" "" { divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "" { divide_by_256:divide_256|temp0[2] } { 0.000ns } { 0.291ns } } } { "uart_clk.v" "" { Text "F:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}