uart_receive.hier_info

Uart port 是一段不错的

|uart_receive
bus[0] <= bus[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bus[1] <= bus[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bus[2] <= bus[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bus[3] <= bus[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bus[4] <= bus[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bus[5] <= bus[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bus[6] <= bus[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bus[7] <= bus[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bit_counter[0] <= bit_counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bit_counter[1] <= bit_counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bit_counter[2] <= bit_counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bit_counter[3] <= bit_counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
error <= error~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
finish_s <= finish_s~reg0.DB_MAX_OUTPUT_PORT_TYPE
serial => counter~4.OUTPUTSELECT
serial => counter~5.OUTPUTSELECT
serial => counter~6.OUTPUTSELECT
serial => counter~7.OUTPUTSELECT
serial => state~1.OUTPUTSELECT
serial => bus_reg[7].DATAIN
clk => finish_s~reg0.CLK
clk => bit_counter[3]~reg0.CLK
clk => bit_counter[2]~reg0.CLK
clk => bit_counter[1]~reg0.CLK
clk => bit_counter[0]~reg0.CLK
clk => counter[3]~reg0.CLK
clk => counter[2]~reg0.CLK
clk => counter[1]~reg0.CLK
clk => counter[0]~reg0.CLK
clk => bus[7]~reg0.CLK
clk => bus[6]~reg0.CLK
clk => bus[5]~reg0.CLK
clk => bus[4]~reg0.CLK
clk => bus[3]~reg0.CLK
clk => bus[2]~reg0.CLK
clk => bus[1]~reg0.CLK
clk => bus[0]~reg0.CLK
clk => error~reg0.CLK
clk => bus_reg[7].CLK
clk => bus_reg[6].CLK
clk => bus_reg[5].CLK
clk => bus_reg[4].CLK
clk => bus_reg[3].CLK
clk => bus_reg[2].CLK
clk => bus_reg[1].CLK
clk => bus_reg[0].CLK
clk => state.CLK
rest => finish_s~reg0.ACLR
rest => bit_counter[3]~reg0.ACLR
rest => bit_counter[2]~reg0.ACLR
rest => bit_counter[1]~reg0.ACLR
rest => bit_counter[0]~reg0.ACLR
rest => counter[3]~reg0.ACLR
rest => counter[2]~reg0.ACLR
rest => counter[1]~reg0.ACLR
rest => counter[0]~reg0.ACLR
rest => state.ACLR