uart_emitter.tan.qmsg

Uart port 是一段不错的

{ "Info" "ITDB_FULL_TCO_RESULT" "clock finish_F finish_F~reg0 6.203 ns register " "Info: tco from clock \"clock\" to destination pin \"finish_F\" through register \"finish_F~reg0\" is 6.203 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.663 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clock 1 CLK PIN_95 22 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 22; CLK Node = 'clock'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { clock } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns finish_F~reg0 2 REG LC3_4_C2 2 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC3_4_C2; Fanout = 2; REG Node = 'finish_F~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.773 ns" { clock finish_F~reg0 } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.52 % ) " "Info: Total cell delay = 0.890 ns ( 53.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns ( 46.48 % ) " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.663 ns" { clock finish_F~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.663 ns" { clock clock~out0 finish_F~reg0 } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.205 ns + Longest register pin " "Info: + Longest register to pin delay is 4.205 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns finish_F~reg0 1 REG LC3_4_C2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC3_4_C2; Fanout = 2; REG Node = 'finish_F~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { finish_F~reg0 } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.634 ns) + CELL(2.410 ns) 4.205 ns finish_F 2 PIN PIN_33 0 " "Info: 2: + IC(1.634 ns) + CELL(2.410 ns) = 4.205 ns; Loc. = PIN_33; Fanout = 0; PIN Node = 'finish_F'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.044 ns" { finish_F~reg0 finish_F } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.571 ns ( 61.14 % ) " "Info: Total cell delay = 2.571 ns ( 61.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.634 ns ( 38.86 % ) " "Info: Total interconnect delay = 1.634 ns ( 38.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.205 ns" { finish_F~reg0 finish_F } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "4.205 ns" { finish_F~reg0 finish_F } { 0.000ns 1.634ns } { 0.161ns 2.410ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.663 ns" { clock finish_F~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.663 ns" { clock clock~out0 finish_F~reg0 } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.205 ns" { finish_F~reg0 finish_F } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "4.205 ns" { finish_F~reg0 finish_F } { 0.000ns 1.634ns } { 0.161ns 2.410ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "bus_reg\[4\] rest clock -1.728 ns register " "Info: th for register \"bus_reg\[4\]\" (data pin = \"rest\", clock pin = \"clock\") is -1.728 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.663 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clock 1 CLK PIN_95 22 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 22; CLK Node = 'clock'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { clock } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns bus_reg\[4\] 2 REG LC9_2_C2 1 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC9_2_C2; Fanout = 1; REG Node = 'bus_reg\[4\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.773 ns" { clock bus_reg[4] } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.52 % ) " "Info: Total cell delay = 0.890 ns ( 53.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns ( 46.48 % ) " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.663 ns" { clock bus_reg[4] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.663 ns" { clock clock~out0 bus_reg[4] } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.364 ns + " "Info: + Micro hold delay of destination is 0.364 ns" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 27 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.755 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.755 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.960 ns) 0.960 ns rest 1 PIN PIN_127 15 " "Info: 1: + IC(0.000 ns) + CELL(0.960 ns) = 0.960 ns; Loc. = PIN_127; Fanout = 15; PIN Node = 'rest'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { rest } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.221 ns) + CELL(0.798 ns) 2.979 ns bus_reg\[7\]~0 2 COMB LC4_2_C2 8 " "Info: 2: + IC(1.221 ns) + CELL(0.798 ns) = 2.979 ns; Loc. = LC4_2_C2; Fanout = 8; COMB Node = 'bus_reg\[7\]~0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "2.019 ns" { rest bus_reg[7]~0 } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.509 ns) 3.755 ns bus_reg\[4\] 3 REG LC9_2_C2 1 " "Info: 3: + IC(0.267 ns) + CELL(0.509 ns) = 3.755 ns; Loc. = LC9_2_C2; Fanout = 1; REG Node = 'bus_reg\[4\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.776 ns" { bus_reg[7]~0 bus_reg[4] } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.267 ns ( 60.37 % ) " "Info: Total cell delay = 2.267 ns ( 60.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.488 ns ( 39.63 % ) " "Info: Total interconnect delay = 1.488 ns ( 39.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "3.755 ns" { rest bus_reg[7]~0 bus_reg[4] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "3.755 ns" { rest rest~out0 bus_reg[7]~0 bus_reg[4] } { 0.000ns 0.000ns 1.221ns 0.267ns } { 0.000ns 0.960ns 0.798ns 0.509ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.663 ns" { clock bus_reg[4] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.663 ns" { clock clock~out0 bus_reg[4] } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "3.755 ns" { rest bus_reg[7]~0 bus_reg[4] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "3.755 ns" { rest rest~out0 bus_reg[7]~0 bus_reg[4] } { 0.000ns 0.000ns 1.221ns 0.267ns } { 0.000ns 0.960ns 0.798ns 0.509ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 11 21:41:07 2006 " "Info: Processing ended: Mon Dec 11 21:41:07 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}