uart_emitter.tan.qmsg

Uart port 是一段不错的

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 3 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock register register state.bit4 serial~reg0 290.02 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 290.02 MHz between source register \"state.bit4\" and destination register \"serial~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 3.448 ns " "Info: fmax restricted to clock pin edge rate 3.448 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.700 ns + Longest register register " "Info: + Longest register to register delay is 2.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns state.bit4 1 REG LC1_3_C2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC1_3_C2; Fanout = 2; REG Node = 'state.bit4'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { state.bit4 } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.967 ns) + CELL(0.694 ns) 1.822 ns Select~148 2 COMB LC5_2_C2 1 " "Info: 2: + IC(0.967 ns) + CELL(0.694 ns) = 1.822 ns; Loc. = LC5_2_C2; Fanout = 1; COMB Node = 'Select~148'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.661 ns" { state.bit4 Select~148 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.532 ns) 2.354 ns Select~146 3 COMB LC6_2_C2 1 " "Info: 3: + IC(0.000 ns) + CELL(0.532 ns) = 2.354 ns; Loc. = LC6_2_C2; Fanout = 1; COMB Node = 'Select~146'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.532 ns" { Select~148 Select~146 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.079 ns) 2.700 ns serial~reg0 4 REG LC8_1_C2 2 " "Info: 4: + IC(0.267 ns) + CELL(0.079 ns) = 2.700 ns; Loc. = LC8_1_C2; Fanout = 2; REG Node = 'serial~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.346 ns" { Select~146 serial~reg0 } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.466 ns ( 54.30 % ) " "Info: Total cell delay = 1.466 ns ( 54.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.234 ns ( 45.70 % ) " "Info: Total interconnect delay = 1.234 ns ( 45.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "2.700 ns" { state.bit4 Select~148 Select~146 serial~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "2.700 ns" { state.bit4 Select~148 Select~146 serial~reg0 } { 0.000ns 0.967ns 0.000ns 0.267ns } { 0.161ns 0.694ns 0.532ns 0.079ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.663 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clock 1 CLK PIN_95 22 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 22; CLK Node = 'clock'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { clock } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns serial~reg0 2 REG LC8_1_C2 2 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC8_1_C2; Fanout = 2; REG Node = 'serial~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.773 ns" { clock serial~reg0 } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.52 % ) " "Info: Total cell delay = 0.890 ns ( 53.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns ( 46.48 % ) " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.663 ns" { clock serial~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.663 ns" { clock clock~out0 serial~reg0 } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.663 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clock 1 CLK PIN_95 22 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 22; CLK Node = 'clock'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { clock } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns state.bit4 2 REG LC1_3_C2 2 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC1_3_C2; Fanout = 2; REG Node = 'state.bit4'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.773 ns" { clock state.bit4 } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.52 % ) " "Info: Total cell delay = 0.890 ns ( 53.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns ( 46.48 % ) " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.663 ns" { clock state.bit4 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.663 ns" { clock clock~out0 state.bit4 } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.663 ns" { clock serial~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.663 ns" { clock clock~out0 serial~reg0 } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.663 ns" { clock state.bit4 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.663 ns" { clock clock~out0 state.bit4 } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 27 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "2.700 ns" { state.bit4 Select~148 Select~146 serial~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "2.700 ns" { state.bit4 Select~148 Select~146 serial~reg0 } { 0.000ns 0.967ns 0.000ns 0.267ns } { 0.161ns 0.694ns 0.532ns 0.079ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.663 ns" { clock serial~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.663 ns" { clock clock~out0 serial~reg0 } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.663 ns" { clock state.bit4 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.663 ns" { clock clock~out0 state.bit4 } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { serial~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "" { serial~reg0 } { 0.000ns } { 0.161ns } } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 27 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "bus_reg\[5\] load_bus_reg clock 5.923 ns register " "Info: tsu for register \"bus_reg\[5\]\" (data pin = \"load_bus_reg\", clock pin = \"clock\") is 5.923 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.388 ns + Longest pin register " "Info: + Longest pin to register delay is 7.388 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.310 ns) 1.310 ns load_bus_reg 1 PIN PIN_142 3 " "Info: 1: + IC(0.000 ns) + CELL(1.310 ns) = 1.310 ns; Loc. = PIN_142; Fanout = 3; PIN Node = 'load_bus_reg'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { load_bus_reg } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.635 ns) + CELL(0.890 ns) 5.835 ns bus_reg\[7\]~0 2 COMB LC4_2_C2 8 " "Info: 2: + IC(3.635 ns) + CELL(0.890 ns) = 5.835 ns; Loc. = LC4_2_C2; Fanout = 8; COMB Node = 'bus_reg\[7\]~0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.525 ns" { load_bus_reg bus_reg[7]~0 } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.509 ns) 7.388 ns bus_reg\[5\] 3 REG LC5_3_C2 1 " "Info: 3: + IC(1.044 ns) + CELL(0.509 ns) = 7.388 ns; Loc. = LC5_3_C2; Fanout = 1; REG Node = 'bus_reg\[5\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.553 ns" { bus_reg[7]~0 bus_reg[5] } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.709 ns ( 36.67 % ) " "Info: Total cell delay = 2.709 ns ( 36.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.679 ns ( 63.33 % ) " "Info: Total interconnect delay = 4.679 ns ( 63.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "7.388 ns" { load_bus_reg bus_reg[7]~0 bus_reg[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "7.388 ns" { load_bus_reg load_bus_reg~out0 bus_reg[7]~0 bus_reg[5] } { 0.000ns 0.000ns 3.635ns 1.044ns } { 0.000ns 1.310ns 0.890ns 0.509ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 27 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.663 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clock 1 CLK PIN_95 22 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 22; CLK Node = 'clock'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { clock } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns bus_reg\[5\] 2 REG LC5_3_C2 1 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC5_3_C2; Fanout = 1; REG Node = 'bus_reg\[5\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.773 ns" { clock bus_reg[5] } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.52 % ) " "Info: Total cell delay = 0.890 ns ( 53.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns ( 46.48 % ) " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.663 ns" { clock bus_reg[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.663 ns" { clock clock~out0 bus_reg[5] } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "7.388 ns" { load_bus_reg bus_reg[7]~0 bus_reg[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "7.388 ns" { load_bus_reg load_bus_reg~out0 bus_reg[7]~0 bus_reg[5] } { 0.000ns 0.000ns 3.635ns 1.044ns } { 0.000ns 1.310ns 0.890ns 0.509ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_emitter" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_emitter.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.663 ns" { clock bus_reg[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.663 ns" { clock clock~out0 bus_reg[5] } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}