usrt_receive.tan.qmsg

Uart port 是一段不错的

{ "Info" "ITDB_FULL_TCO_RESULT" "clk load sample_counter\[0\]~reg0 11.729 ns register " "Info: tco from clock \"clk\" to destination pin \"load\" through register \"sample_counter\[0\]~reg0\" is 11.729 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.658 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK PIN_95 27 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 27; CLK Node = 'clk'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { clk } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.768 ns) + CELL(0.000 ns) 1.658 ns sample_counter\[0\]~reg0 2 REG LC6_10_D1 5 " "Info: 2: + IC(0.768 ns) + CELL(0.000 ns) = 1.658 ns; Loc. = LC6_10_D1; Fanout = 5; REG Node = 'sample_counter\[0\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.768 ns" { clk sample_counter[0]~reg0 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.68 % ) " "Info: Total cell delay = 0.890 ns ( 53.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.768 ns ( 46.32 % ) " "Info: Total interconnect delay = 0.768 ns ( 46.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.658 ns" { clk sample_counter[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.658 ns" { clk clk~out0 sample_counter[0]~reg0 } { 0.000ns 0.000ns 0.768ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.736 ns + Longest register pin " "Info: + Longest register to pin delay is 9.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns sample_counter\[0\]~reg0 1 REG LC6_10_D1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC6_10_D1; Fanout = 5; REG Node = 'sample_counter\[0\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { sample_counter[0]~reg0 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(0.890 ns) 1.335 ns rtl~0 2 COMB LC1_10_D1 8 " "Info: 2: + IC(0.284 ns) + CELL(0.890 ns) = 1.335 ns; Loc. = LC1_10_D1; Fanout = 8; COMB Node = 'rtl~0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.174 ns" { sample_counter[0]~reg0 rtl~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.653 ns) + CELL(0.358 ns) 4.346 ns read_not_ready_out~42 3 COMB LC8_8_A2 4 " "Info: 3: + IC(2.653 ns) + CELL(0.358 ns) = 4.346 ns; Loc. = LC8_8_A2; Fanout = 4; COMB Node = 'read_not_ready_out~42'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "3.011 ns" { rtl~0 read_not_ready_out~42 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.263 ns) + CELL(0.358 ns) 4.967 ns load~29 4 COMB LC9_8_A2 9 " "Info: 4: + IC(0.263 ns) + CELL(0.358 ns) = 4.967 ns; Loc. = LC9_8_A2; Fanout = 9; COMB Node = 'load~29'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.621 ns" { read_not_ready_out~42 load~29 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.279 ns) + CELL(2.490 ns) 9.736 ns load 5 PIN PIN_112 0 " "Info: 5: + IC(2.279 ns) + CELL(2.490 ns) = 9.736 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'load'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.769 ns" { load~29 load } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.257 ns ( 43.72 % ) " "Info: Total cell delay = 4.257 ns ( 43.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.479 ns ( 56.28 % ) " "Info: Total interconnect delay = 5.479 ns ( 56.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "9.736 ns" { sample_counter[0]~reg0 rtl~0 read_not_ready_out~42 load~29 load } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "9.736 ns" { sample_counter[0]~reg0 rtl~0 read_not_ready_out~42 load~29 load } { 0.000ns 0.284ns 2.653ns 0.263ns 2.279ns } { 0.161ns 0.890ns 0.358ns 0.358ns 2.490ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.658 ns" { clk sample_counter[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.658 ns" { clk clk~out0 sample_counter[0]~reg0 } { 0.000ns 0.000ns 0.768ns } { 0.000ns 0.890ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "9.736 ns" { sample_counter[0]~reg0 rtl~0 read_not_ready_out~42 load~29 load } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "9.736 ns" { sample_counter[0]~reg0 rtl~0 read_not_ready_out~42 load~29 load } { 0.000ns 0.284ns 2.653ns 0.263ns 2.279ns } { 0.161ns 0.890ns 0.358ns 0.358ns 2.490ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "serial load 11.671 ns Longest " "Info: Longest tpd from source pin \"serial\" to destination pin \"load\" is 11.671 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.310 ns) 1.310 ns serial 1 PIN PIN_62 8 " "Info: 1: + IC(0.000 ns) + CELL(1.310 ns) = 1.310 ns; Loc. = PIN_62; Fanout = 8; PIN Node = 'serial'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { serial } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.794 ns) + CELL(0.798 ns) 6.902 ns load~29 2 COMB LC9_8_A2 9 " "Info: 2: + IC(4.794 ns) + CELL(0.798 ns) = 6.902 ns; Loc. = LC9_8_A2; Fanout = 9; COMB Node = 'load~29'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "5.592 ns" { serial load~29 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.279 ns) + CELL(2.490 ns) 11.671 ns load 3 PIN PIN_112 0 " "Info: 3: + IC(2.279 ns) + CELL(2.490 ns) = 11.671 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'load'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.769 ns" { load~29 load } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.598 ns ( 39.40 % ) " "Info: Total cell delay = 4.598 ns ( 39.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.073 ns ( 60.60 % ) " "Info: Total interconnect delay = 7.073 ns ( 60.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "11.671 ns" { serial load~29 load } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "11.671 ns" { serial serial~out0 load~29 load } { 0.000ns 0.000ns 4.794ns 2.279ns } { 0.000ns 1.310ns 0.798ns 2.490ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "date_bus\[0\]~reg0 read_not_ready_in clk -4.071 ns register " "Info: th for register \"date_bus\[0\]~reg0\" (data pin = \"read_not_ready_in\", clock pin = \"clk\") is -4.071 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.673 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK PIN_95 27 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 27; CLK Node = 'clk'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { clk } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns date_bus\[0\]~reg0 2 REG LC3_8_A2 1 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC3_8_A2; Fanout = 1; REG Node = 'date_bus\[0\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.783 ns" { clk date_bus[0]~reg0 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.20 % ) " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 46.80 % ) " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.673 ns" { clk date_bus[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.673 ns" { clk clk~out0 date_bus[0]~reg0 } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.364 ns + " "Info: + Micro hold delay of destination is 0.364 ns" {  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.108 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.108 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns read_not_ready_in 1 PIN PIN_7 3 " "Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = PIN_7; Fanout = 3; PIN Node = 'read_not_ready_in'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { read_not_ready_in } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.223 ns) + CELL(0.890 ns) 5.353 ns load~29 2 COMB LC9_8_A2 9 " "Info: 2: + IC(3.223 ns) + CELL(0.890 ns) = 5.353 ns; Loc. = LC9_8_A2; Fanout = 9; COMB Node = 'load~29'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.113 ns" { read_not_ready_in load~29 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.509 ns) 6.108 ns date_bus\[0\]~reg0 3 REG LC3_8_A2 1 " "Info: 3: + IC(0.246 ns) + CELL(0.509 ns) = 6.108 ns; Loc. = LC3_8_A2; Fanout = 1; REG Node = 'date_bus\[0\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.755 ns" { load~29 date_bus[0]~reg0 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.639 ns ( 43.21 % ) " "Info: Total cell delay = 2.639 ns ( 43.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.469 ns ( 56.79 % ) " "Info: Total interconnect delay = 3.469 ns ( 56.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "6.108 ns" { read_not_ready_in load~29 date_bus[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "6.108 ns" { read_not_ready_in read_not_ready_in~out0 load~29 date_bus[0]~reg0 } { 0.000ns 0.000ns 3.223ns 0.246ns } { 0.000ns 1.240ns 0.890ns 0.509ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.673 ns" { clk date_bus[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.673 ns" { clk clk~out0 date_bus[0]~reg0 } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "6.108 ns" { read_not_ready_in load~29 date_bus[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "6.108 ns" { read_not_ready_in read_not_ready_in~out0 load~29 date_bus[0]~reg0 } { 0.000ns 0.000ns 3.223ns 0.246ns } { 0.000ns 1.240ns 0.890ns 0.509ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 11 21:46:28 2006 " "Info: Processing ended: Mon Dec 11 21:46:28 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}