usrt_receive.tan.qmsg

Uart port 是一段不错的

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 8 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register sample_counter\[0\]~reg0 register bit_counter\[3\]~reg0 140.1 MHz 7.138 ns Internal " "Info: Clock \"clk\" has Internal fmax of 140.1 MHz between source register \"sample_counter\[0\]~reg0\" and destination register \"bit_counter\[3\]~reg0\" (period= 7.138 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.620 ns + Longest register register " "Info: + Longest register to register delay is 6.620 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns sample_counter\[0\]~reg0 1 REG LC6_10_D1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC6_10_D1; Fanout = 5; REG Node = 'sample_counter\[0\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { sample_counter[0]~reg0 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(0.890 ns) 1.335 ns rtl~0 2 COMB LC1_10_D1 8 " "Info: 2: + IC(0.284 ns) + CELL(0.890 ns) = 1.335 ns; Loc. = LC1_10_D1; Fanout = 8; COMB Node = 'rtl~0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.174 ns" { sample_counter[0]~reg0 rtl~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.701 ns) + CELL(0.358 ns) 4.394 ns inc_bit_counter~11 3 COMB LC1_7_A2 12 " "Info: 3: + IC(2.701 ns) + CELL(0.358 ns) = 4.394 ns; Loc. = LC1_7_A2; Fanout = 12; COMB Node = 'inc_bit_counter~11'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "3.059 ns" { rtl~0 inc_bit_counter~11 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.298 ns) + CELL(0.670 ns) 5.362 ns add~126 4 COMB LC3_6_A2 2 " "Info: 4: + IC(0.298 ns) + CELL(0.670 ns) = 5.362 ns; Loc. = LC3_6_A2; Fanout = 2; COMB Node = 'add~126'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.968 ns" { inc_bit_counter~11 add~126 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 5.477 ns add~122 5 COMB LC4_6_A2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.115 ns) = 5.477 ns; Loc. = LC4_6_A2; Fanout = 2; COMB Node = 'add~122'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.115 ns" { add~126 add~122 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 5.592 ns add~118 6 COMB LC5_6_A2 1 " "Info: 6: + IC(0.000 ns) + CELL(0.115 ns) = 5.592 ns; Loc. = LC5_6_A2; Fanout = 1; COMB Node = 'add~118'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.115 ns" { add~122 add~118 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.668 ns) 6.260 ns add~112 7 COMB LC6_6_A2 1 " "Info: 7: + IC(0.000 ns) + CELL(0.668 ns) = 6.260 ns; Loc. = LC6_6_A2; Fanout = 1; COMB Node = 'add~112'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.668 ns" { add~118 add~112 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.281 ns) + CELL(0.079 ns) 6.620 ns bit_counter\[3\]~reg0 8 REG LC7_6_A2 3 " "Info: 8: + IC(0.281 ns) + CELL(0.079 ns) = 6.620 ns; Loc. = LC7_6_A2; Fanout = 3; REG Node = 'bit_counter\[3\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.360 ns" { add~112 bit_counter[3]~reg0 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.056 ns ( 46.16 % ) " "Info: Total cell delay = 3.056 ns ( 46.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.564 ns ( 53.84 % ) " "Info: Total interconnect delay = 3.564 ns ( 53.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "6.620 ns" { sample_counter[0]~reg0 rtl~0 inc_bit_counter~11 add~126 add~122 add~118 add~112 bit_counter[3]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "6.620 ns" { sample_counter[0]~reg0 rtl~0 inc_bit_counter~11 add~126 add~122 add~118 add~112 bit_counter[3]~reg0 } { 0.000ns 0.284ns 2.701ns 0.298ns 0.000ns 0.000ns 0.000ns 0.281ns } { 0.161ns 0.890ns 0.358ns 0.670ns 0.115ns 0.115ns 0.668ns 0.079ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.015 ns - Smallest " "Info: - Smallest clock skew is 0.015 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.673 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK PIN_95 27 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 27; CLK Node = 'clk'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { clk } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns bit_counter\[3\]~reg0 2 REG LC7_6_A2 3 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC7_6_A2; Fanout = 3; REG Node = 'bit_counter\[3\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.783 ns" { clk bit_counter[3]~reg0 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.20 % ) " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 46.80 % ) " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.673 ns" { clk bit_counter[3]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.673 ns" { clk clk~out0 bit_counter[3]~reg0 } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.658 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK PIN_95 27 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 27; CLK Node = 'clk'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { clk } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.768 ns) + CELL(0.000 ns) 1.658 ns sample_counter\[0\]~reg0 2 REG LC6_10_D1 5 " "Info: 2: + IC(0.768 ns) + CELL(0.000 ns) = 1.658 ns; Loc. = LC6_10_D1; Fanout = 5; REG Node = 'sample_counter\[0\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.768 ns" { clk sample_counter[0]~reg0 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.68 % ) " "Info: Total cell delay = 0.890 ns ( 53.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.768 ns ( 46.32 % ) " "Info: Total interconnect delay = 0.768 ns ( 46.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.658 ns" { clk sample_counter[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.658 ns" { clk clk~out0 sample_counter[0]~reg0 } { 0.000ns 0.000ns 0.768ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.673 ns" { clk bit_counter[3]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.673 ns" { clk clk~out0 bit_counter[3]~reg0 } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.658 ns" { clk sample_counter[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.658 ns" { clk clk~out0 sample_counter[0]~reg0 } { 0.000ns 0.000ns 0.768ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" {  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "6.620 ns" { sample_counter[0]~reg0 rtl~0 inc_bit_counter~11 add~126 add~122 add~118 add~112 bit_counter[3]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "6.620 ns" { sample_counter[0]~reg0 rtl~0 inc_bit_counter~11 add~126 add~122 add~118 add~112 bit_counter[3]~reg0 } { 0.000ns 0.284ns 2.701ns 0.298ns 0.000ns 0.000ns 0.000ns 0.281ns } { 0.161ns 0.890ns 0.358ns 0.670ns 0.115ns 0.115ns 0.668ns 0.079ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.673 ns" { clk bit_counter[3]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.673 ns" { clk clk~out0 bit_counter[3]~reg0 } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.658 ns" { clk sample_counter[0]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.658 ns" { clk clk~out0 sample_counter[0]~reg0 } { 0.000ns 0.000ns 0.768ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "sample_counter\[3\]~reg0 serial clk 7.352 ns register " "Info: tsu for register \"sample_counter\[3\]~reg0\" (data pin = \"serial\", clock pin = \"clk\") is 7.352 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.812 ns + Longest pin register " "Info: + Longest pin to register delay is 8.812 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.310 ns) 1.310 ns serial 1 PIN PIN_62 8 " "Info: 1: + IC(0.000 ns) + CELL(1.310 ns) = 1.310 ns; Loc. = PIN_62; Fanout = 8; PIN Node = 'serial'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { serial } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.685 ns) + CELL(0.890 ns) 5.885 ns Select~159 2 COMB LC10_10_D1 1 " "Info: 2: + IC(3.685 ns) + CELL(0.890 ns) = 5.885 ns; Loc. = LC10_10_D1; Fanout = 1; COMB Node = 'Select~159'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.575 ns" { serial Select~159 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.274 ns) + CELL(0.358 ns) 6.517 ns Select~160 3 COMB LC5_10_D1 3 " "Info: 3: + IC(0.274 ns) + CELL(0.358 ns) = 6.517 ns; Loc. = LC5_10_D1; Fanout = 3; COMB Node = 'Select~160'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.632 ns" { Select~159 Select~160 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.274 ns) + CELL(1.122 ns) 7.913 ns sample_counter\[0\]~40 4 COMB LC6_10_D1 2 " "Info: 4: + IC(0.274 ns) + CELL(1.122 ns) = 7.913 ns; Loc. = LC6_10_D1; Fanout = 2; COMB Node = 'sample_counter\[0\]~40'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.396 ns" { Select~160 sample_counter[0]~40 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 8.028 ns sample_counter\[1\]~43 5 COMB LC7_10_D1 2 " "Info: 5: + IC(0.000 ns) + CELL(0.115 ns) = 8.028 ns; Loc. = LC7_10_D1; Fanout = 2; COMB Node = 'sample_counter\[1\]~43'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.115 ns" { sample_counter[0]~40 sample_counter[1]~43 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 8.143 ns sample_counter\[2\]~37 6 COMB LC8_10_D1 1 " "Info: 6: + IC(0.000 ns) + CELL(0.115 ns) = 8.143 ns; Loc. = LC8_10_D1; Fanout = 1; COMB Node = 'sample_counter\[2\]~37'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.115 ns" { sample_counter[1]~43 sample_counter[2]~37 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.669 ns) 8.812 ns sample_counter\[3\]~reg0 7 REG LC9_10_D1 4 " "Info: 7: + IC(0.000 ns) + CELL(0.669 ns) = 8.812 ns; Loc. = LC9_10_D1; Fanout = 4; REG Node = 'sample_counter\[3\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.669 ns" { sample_counter[2]~37 sample_counter[3]~reg0 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.579 ns ( 51.96 % ) " "Info: Total cell delay = 4.579 ns ( 51.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.233 ns ( 48.04 % ) " "Info: Total interconnect delay = 4.233 ns ( 48.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "8.812 ns" { serial Select~159 Select~160 sample_counter[0]~40 sample_counter[1]~43 sample_counter[2]~37 sample_counter[3]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "8.812 ns" { serial serial~out0 Select~159 Select~160 sample_counter[0]~40 sample_counter[1]~43 sample_counter[2]~37 sample_counter[3]~reg0 } { 0.000ns 0.000ns 3.685ns 0.274ns 0.274ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.310ns 0.890ns 0.358ns 1.122ns 0.115ns 0.115ns 0.669ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" {  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.658 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 1.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK PIN_95 27 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 27; CLK Node = 'clk'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { clk } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.768 ns) + CELL(0.000 ns) 1.658 ns sample_counter\[3\]~reg0 2 REG LC9_10_D1 4 " "Info: 2: + IC(0.768 ns) + CELL(0.000 ns) = 1.658 ns; Loc. = LC9_10_D1; Fanout = 4; REG Node = 'sample_counter\[3\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.768 ns" { clk sample_counter[3]~reg0 } "NODE_NAME" } "" } } { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.68 % ) " "Info: Total cell delay = 0.890 ns ( 53.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.768 ns ( 46.32 % ) " "Info: Total interconnect delay = 0.768 ns ( 46.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.658 ns" { clk sample_counter[3]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.658 ns" { clk clk~out0 sample_counter[3]~reg0 } { 0.000ns 0.000ns 0.768ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "8.812 ns" { serial Select~159 Select~160 sample_counter[0]~40 sample_counter[1]~43 sample_counter[2]~37 sample_counter[3]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "8.812 ns" { serial serial~out0 Select~159 Select~160 sample_counter[0]~40 sample_counter[1]~43 sample_counter[2]~37 sample_counter[3]~reg0 } { 0.000ns 0.000ns 3.685ns 0.274ns 0.274ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.310ns 0.890ns 0.358ns 1.122ns 0.115ns 0.115ns 0.669ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "usrt_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/usrt_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.658 ns" { clk sample_counter[3]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.658 ns" { clk clk~out0 sample_counter[3]~reg0 } { 0.000ns 0.000ns 0.768ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}