uart_top.map.qmsg

Uart port 是一段不错的

{ "Warning" "WSGN_SEARCH_FILE" "uart_receive.v 1 1 " "Warning: Using design file uart_receive.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 uart_receive " "Info: Found entity 1: uart_receive" {  } { { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_receive uart_receive:uart_receiver_a " "Info: Elaborating entity \"uart_receive\" for hierarchy \"uart_receive:uart_receiver_a\"" {  } { { "uart_top.v" "uart_receiver_a" { Text "E:/verilog/uart/uart_top.v" 23 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "uart_receive:uart_receiver_a\|error High " "Info: Power-up level of register \"uart_receive:uart_receiver_a\|error\" is not specified -- using power-up level of High to minimize register" {  } { { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 6 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "uart_receive:uart_receiver_a\|error data_in VCC " "Warning: Reduced register \"uart_receive:uart_receiver_a\|error\" with stuck data_in port to stuck value VCC" {  } { { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 6 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|uart_top\|uart_emitter:uart_emitter_a\|state 12 " "Info: State machine \"\|uart_top\|uart_emitter:uart_emitter_a\|state\" contains 12 states" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|uart_top\|uart_emitter:uart_emitter_a\|state " "Info: Selected Auto state machine encoding method for state machine \"\|uart_top\|uart_emitter:uart_emitter_a\|state\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|uart_top\|uart_emitter:uart_emitter_a\|state " "Info: Encoding result for state machine \"\|uart_top\|uart_emitter:uart_emitter_a\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "12 " "Info: Completed encoding using 12 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_emitter:uart_emitter_a\|state.over " "Info: Encoded state bit \"uart_emitter:uart_emitter_a\|state.over\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_emitter:uart_emitter_a\|state.bit0 " "Info: Encoded state bit \"uart_emitter:uart_emitter_a\|state.bit0\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_emitter:uart_emitter_a\|state.bit1 " "Info: Encoded state bit \"uart_emitter:uart_emitter_a\|state.bit1\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_emitter:uart_emitter_a\|state.bit2 " "Info: Encoded state bit \"uart_emitter:uart_emitter_a\|state.bit2\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_emitter:uart_emitter_a\|state.bit3 " "Info: Encoded state bit \"uart_emitter:uart_emitter_a\|state.bit3\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_emitter:uart_emitter_a\|state.bit4 " "Info: Encoded state bit \"uart_emitter:uart_emitter_a\|state.bit4\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_emitter:uart_emitter_a\|state.bit5 " "Info: Encoded state bit \"uart_emitter:uart_emitter_a\|state.bit5\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_emitter:uart_emitter_a\|state.bit6 " "Info: Encoded state bit \"uart_emitter:uart_emitter_a\|state.bit6\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_emitter:uart_emitter_a\|state.bit7 " "Info: Encoded state bit \"uart_emitter:uart_emitter_a\|state.bit7\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_emitter:uart_emitter_a\|state.bit8 " "Info: Encoded state bit \"uart_emitter:uart_emitter_a\|state.bit8\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_emitter:uart_emitter_a\|state.bit9 " "Info: Encoded state bit \"uart_emitter:uart_emitter_a\|state.bit9\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart_emitter:uart_emitter_a\|state.idle " "Info: Encoded state bit \"uart_emitter:uart_emitter_a\|state.idle\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_emitter:uart_emitter_a\|state.idle 000000000000 " "Info: State \"\|uart_top\|uart_emitter:uart_emitter_a\|state.idle\" uses code string \"000000000000\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_emitter:uart_emitter_a\|state.bit9 000000000011 " "Info: State \"\|uart_top\|uart_emitter:uart_emitter_a\|state.bit9\" uses code string \"000000000011\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_emitter:uart_emitter_a\|state.bit8 000000000101 " "Info: State \"\|uart_top\|uart_emitter:uart_emitter_a\|state.bit8\" uses code string \"000000000101\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_emitter:uart_emitter_a\|state.bit7 000000001001 " "Info: State \"\|uart_top\|uart_emitter:uart_emitter_a\|state.bit7\" uses code string \"000000001001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_emitter:uart_emitter_a\|state.bit6 000000010001 " "Info: State \"\|uart_top\|uart_emitter:uart_emitter_a\|state.bit6\" uses code string \"000000010001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_emitter:uart_emitter_a\|state.bit5 000000100001 " "Info: State \"\|uart_top\|uart_emitter:uart_emitter_a\|state.bit5\" uses code string \"000000100001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_emitter:uart_emitter_a\|state.bit4 000001000001 " "Info: State \"\|uart_top\|uart_emitter:uart_emitter_a\|state.bit4\" uses code string \"000001000001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_emitter:uart_emitter_a\|state.bit3 000010000001 " "Info: State \"\|uart_top\|uart_emitter:uart_emitter_a\|state.bit3\" uses code string \"000010000001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_emitter:uart_emitter_a\|state.bit2 000100000001 " "Info: State \"\|uart_top\|uart_emitter:uart_emitter_a\|state.bit2\" uses code string \"000100000001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_emitter:uart_emitter_a\|state.bit1 001000000001 " "Info: State \"\|uart_top\|uart_emitter:uart_emitter_a\|state.bit1\" uses code string \"001000000001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_emitter:uart_emitter_a\|state.bit0 010000000001 " "Info: State \"\|uart_top\|uart_emitter:uart_emitter_a\|state.bit0\" uses code string \"010000000001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_top\|uart_emitter:uart_emitter_a\|state.over 100000000001 " "Info: State \"\|uart_top\|uart_emitter:uart_emitter_a\|state.over\" uses code string \"100000000001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 5 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "error VCC " "Warning: Pin \"error\" stuck at VCC" {  } { { "uart_top.v" "" { Text "E:/verilog/uart/uart_top.v" 15 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "121 " "Info: Implemented 121 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "14 " "Info: Implemented 14 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "22 " "Info: Implemented 22 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "85 " "Info: Implemented 85 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 12 00:16:18 2007 " "Info: Processing ended: Mon Mar 12 00:16:18 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}