uart_top.map.qmsg

Uart port 是一段不错的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 12 00:16:09 2007 " "Info: Processing started: Mon Mar 12 00:16:09 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uart_top -c uart_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart_top -c uart_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file uart_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_top " "Info: Found entity 1: uart_top" {  } { { "uart_top.v" "" { Text "E:/verilog/uart/uart_top.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "uart_top " "Info: Elaborating entity \"uart_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "uart_clk.v 3 3 " "Warning: Using design file uart_clk.v, which is not specified as a design file for the current project, but contains definitions for 3 design units and 3 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 uart_clk " "Info: Found entity 1: uart_clk" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 divide_by_13 " "Info: Found entity 2: divide_by_13" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 17 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 divide_by_256 " "Info: Found entity 3: divide_by_256" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_clk uart_clk:uart_clk_gen_a " "Info: Elaborating entity \"uart_clk\" for hierarchy \"uart_clk:uart_clk_gen_a\"" {  } { { "uart_top.v" "uart_clk_gen_a" { Text "E:/verilog/uart/uart_top.v" 21 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "temp uart_clk.v(9) " "Info (10035): Verilog HDL or VHDL information at uart_clk.v(9): object \"temp\" declared but not used" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 9 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "temp0 uart_clk.v(10) " "Info (10035): Verilog HDL or VHDL information at uart_clk.v(10): object \"temp0\" declared but not used" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 10 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divide_by_13 uart_clk:uart_clk_gen_a\|divide_by_13:divide_13 " "Info: Elaborating entity \"divide_by_13\" for hierarchy \"uart_clk:uart_clk_gen_a\|divide_by_13:divide_13\"" {  } { { "uart_clk.v" "divide_13" { Text "E:/verilog/uart/uart_clk.v" 13 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divide_by_256 uart_clk:uart_clk_gen_a\|divide_by_256:divide_256 " "Info: Elaborating entity \"divide_by_256\" for hierarchy \"uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\"" {  } { { "uart_clk.v" "divide_256" { Text "E:/verilog/uart/uart_clk.v" 14 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "uart_emitter.v 1 1 " "Warning: Using design file uart_emitter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 uart_emitter " "Info: Found entity 1: uart_emitter" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_emitter uart_emitter:uart_emitter_a " "Info: Elaborating entity \"uart_emitter\" for hierarchy \"uart_emitter:uart_emitter_a\"" {  } { { "uart_top.v" "uart_emitter_a" { Text "E:/verilog/uart/uart_top.v" 22 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}