uart_clk.sim.vwf

Uart port 是一段不错的

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	SIMULATION_TIME = 10000000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("clock")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("rest")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("sample_clock")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("sel_baud_rate")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 3;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("sel_baud_rate[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sel_baud_rate";
}

SIGNAL("sel_baud_rate[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sel_baud_rate";
}

SIGNAL("sel_baud_rate[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sel_baud_rate";
}

SIGNAL("sys_clock")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

TRANSITION_LIST("clock")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 208704.222;
		NODE
		{
			REPEAT = 23;
			LEVEL 1 FOR 208000.0;
			LEVEL 0 FOR 208000.0;
		}
		LEVEL 1 FOR 208000.0;
		LEVEL 0 FOR 15295.778;
	}
}

TRANSITION_LIST("rest")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 65.0;
		LEVEL 1 FOR 1370.0;
		LEVEL 0 FOR 9998565.0;
	}
}

TRANSITION_LIST("sample_clock")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1456708.234;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 1664000.0;
			LEVEL 0 FOR 1664000.0;
		}
		LEVEL 1 FOR 1664000.0;
		LEVEL 0 FOR 223291.766;
	}
}

TRANSITION_LIST("sel_baud_rate[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 10000000.0;
	}
}

TRANSITION_LIST("sel_baud_rate[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 10000000.0;
	}
}

TRANSITION_LIST("sel_baud_rate[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 10000000.0;
	}
}

TRANSITION_LIST("sys_clock")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 80000;
			LEVEL 0 FOR 62.5;
			LEVEL 1 FOR 62.5;
		}
	}
}

DISPLAY_LINE
{
	CHANNEL = "rest";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "sel_baud_rate";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
	CHILDREN = 2, 3, 4;
}

DISPLAY_LINE
{
	CHANNEL = "sel_baud_rate[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 2;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "sel_baud_rate[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 3;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "sel_baud_rate[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "sys_clock";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 5;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "sample_clock";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 6;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "clock";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 7;
	TREE_LEVEL = 0;
}

TIME_BAR
{
	TIME = 11150;
	MASTER = TRUE;
}
;