uart_receive.fit.qmsg

Uart port 是一段不错的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 12 00:30:09 2006 " "Info: Processing started: Tue Dec 12 00:30:09 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off uart_receive -c uart_receive " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off uart_receive -c uart_receive" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "uart_receive EP20K30ETC144-1 " "Info: Automatically selected device EP20K30ETC144-1 for design uart_receive" {  } {  } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "clk automatically " "Info: Promoted cell \"clk\" to global signal automatically" {  } {  } 0 0 "Promoted cell \"%1!s!\" to global signal %2!s!" 0 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "rest automatically " "Info: Promoted cell \"rest\" to global signal automatically" {  } {  } 0 0 "Promoted cell \"%1!s!\" to global signal %2!s!" 0 0}
{ "Info" "IFIT_FIT_ATTEMPT" "1 Tue Dec 12 2006 00:30:18 " "Info: Started fitting attempt 1 on Tue Dec 12 2006 at 00:30:18" {  } {  } 0 0 "Started fitting attempt %1!d! on %2!s! at %3!s!" 0 0}
{ "Warning" "WFITAPI_FITAPI_WARNING_VPR_PERFORMANCE_MAY_DEGRADE_AS_FDI_IS_NOT_LOADED" "" "Warning: Performance of this circuit may degrade because the Fitter Delay Information is not loaded." {  } {  } 0 0 "Performance of this circuit may degrade because the Fitter Delay Information is not loaded." 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACER_ESTIMATED_ROUTING_RESOURCE_USAGE" "" "Info: Design requires the following device routing resources:" { { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_COL_FSTTRK" "0 " "Info: Overall column FastTrack interconnect = 0%" {  } {  } 0 0 "Overall column FastTrack interconnect = %1!d!%%" 0 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_ROW_FSTTRK" "0 " "Info: Overall row FastTrack interconnect = 0%" {  } {  } 0 0 "Overall row FastTrack interconnect = %1!d!%%" 0 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_COL_FSTTRK" "0 " "Info: Maximum column FastTrack interconnect = 0%" {  } {  } 0 0 "Maximum column FastTrack interconnect = %1!d!%%" 0 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_ROW_FSTTRK" "1 " "Info: Maximum row FastTrack interconnect = 1%" {  } {  } 0 0 "Maximum row FastTrack interconnect = %1!d!%%" 0 0}  } {  } 0 0 "Design requires the following device routing resources:" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.324 ns register register " "Info: Estimated most critical path is register to register delay of 4.324 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns counter\[3\]~reg0 1 REG LAB_6_A2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LAB_6_A2; Fanout = 4; REG Node = 'counter\[3\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { counter[3]~reg0 } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.890 ns) 1.297 ns rtl~1 2 COMB LAB_6_A2 6 " "Info: 2: + IC(0.246 ns) + CELL(0.890 ns) = 1.297 ns; Loc. = LAB_6_A2; Fanout = 6; COMB Node = 'rtl~1'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.136 ns" { counter[3]~reg0 rtl~1 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.890 ns) 2.433 ns bit_counter\[0\]~162 3 COMB LAB_6_A2 7 " "Info: 3: + IC(0.246 ns) + CELL(0.890 ns) = 2.433 ns; Loc. = LAB_6_A2; Fanout = 7; COMB Node = 'bit_counter\[0\]~162'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.136 ns" { rtl~1 bit_counter[0]~162 } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.890 ns) 3.569 ns bus\[0\]~15 4 COMB LAB_5_A2 8 " "Info: 4: + IC(0.246 ns) + CELL(0.890 ns) = 3.569 ns; Loc. = LAB_5_A2; Fanout = 8; COMB Node = 'bus\[0\]~15'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.136 ns" { bit_counter[0]~162 bus[0]~15 } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.509 ns) 4.324 ns bus\[0\]~reg0 5 REG LAB_5_A2 1 " "Info: 5: + IC(0.246 ns) + CELL(0.509 ns) = 4.324 ns; Loc. = LAB_5_A2; Fanout = 1; REG Node = 'bus\[0\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.755 ns" { bus[0]~15 bus[0]~reg0 } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.340 ns ( 77.24 % ) " "Info: Total cell delay = 3.340 ns ( 77.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.984 ns ( 22.76 % ) " "Info: Total interconnect delay = 0.984 ns ( 22.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.324 ns" { counter[3]~reg0 rtl~1 bit_counter[0]~162 bus[0]~15 bus[0]~reg0 } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 12 00:30:25 2006 " "Info: Processing ended: Tue Dec 12 00:30:25 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Info: Elapsed time: 00:00:18" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}