uart_emitter.hier_info

Uart port 是一段不错的

|uart_emitter
serial <= serial~reg0.DB_MAX_OUTPUT_PORT_TYPE
finish_F <= finish_F~reg0.DB_MAX_OUTPUT_PORT_TYPE
bus[0] => bus_reg[0].DATAIN
bus[1] => bus_reg[1].DATAIN
bus[2] => bus_reg[2].DATAIN
bus[3] => bus_reg[3].DATAIN
bus[4] => bus_reg[4].DATAIN
bus[5] => bus_reg[5].DATAIN
bus[6] => bus_reg[6].DATAIN
bus[7] => bus_reg[7].DATAIN
clock => serial~reg0.CLK
clock => finish_F~reg0.CLK
clock => bus_reg[7].CLK
clock => bus_reg[6].CLK
clock => bus_reg[5].CLK
clock => bus_reg[4].CLK
clock => bus_reg[3].CLK
clock => bus_reg[2].CLK
clock => bus_reg[1].CLK
clock => bus_reg[0].CLK
clock => state~1.IN1
rest => serial~reg0.PRESET
rest => finish_F~reg0.ACLR
rest => state~2.IN1
load_bus_reg => state~0.DATAB
load_bus_reg => Select~0.IN2