uart_clk.hif

Uart port 是一段不错的

Version 5.1 Build 176 10/26/2005 SJ Full Version
5
341
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
# entity
uart_clk
# storage
db|uart_clk.(0).cnf
db|uart_clk.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_clk.v
d465a217e258e522a345d3a4adc4a2
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
divide_by_13
# storage
db|uart_clk.(1).cnf
db|uart_clk.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_clk.v
d465a217e258e522a345d3a4adc4a2
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
divide_by_13:divide_13
}
# end
# entity
divide_by_256
# storage
db|uart_clk.(2).cnf
db|uart_clk.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_clk.v
d465a217e258e522a345d3a4adc4a2
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
divide_by_256:divide_256
}
# end
# complete