uart_top.hif

Uart port 是一段不错的

Version 5.1 Build 176 10/26/2005 SJ Full Version
5
2006
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
# entity
uart_clk
# storage
db|uart_top.(1).cnf
db|uart_top.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_clk.v
d465a217e258e522a345d3a4adc4a2
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
uart_clk:uart_clk_gen_a
}
# end
# entity
divide_by_13
# storage
db|uart_top.(2).cnf
db|uart_top.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_clk.v
d465a217e258e522a345d3a4adc4a2
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
uart_clk:uart_clk_gen_a|divide_by_13:divide_13
}
# end
# entity
divide_by_256
# storage
db|uart_top.(3).cnf
db|uart_top.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_clk.v
d465a217e258e522a345d3a4adc4a2
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
uart_clk:uart_clk_gen_a|divide_by_256:divide_256
}
# end
# entity
uart_emitter
# storage
db|uart_top.(4).cnf
db|uart_top.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_emitter.v
4dab8cb9637da37edf84d1e86e32af3
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
idle
0000
PARAMETER_BIN
DEF
bit0
0001
PARAMETER_BIN
DEF
bit1
0011
PARAMETER_BIN
DEF
bit2
0010
PARAMETER_BIN
DEF
bit3
0110
PARAMETER_BIN
DEF
bit4
0111
PARAMETER_BIN
DEF
bit5
0101
PARAMETER_BIN
DEF
bit6
0100
PARAMETER_BIN
DEF
bit7
1100
PARAMETER_BIN
DEF
bit8
1101
PARAMETER_BIN
DEF
bit9
1111
PARAMETER_BIN
DEF
over
1110
PARAMETER_BIN
DEF
}
# hierarchies {
uart_emitter:uart_emitter_a
}
# end
# entity
usrt_receive
# storage
db|uart_top.(5).cnf
db|uart_top.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
usrt_receive.v
e77ba832e1a968d85cee3a2c45f7ac
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
count_size
3
PARAMETER_DEC
DEF
word_size
8
PARAMETER_DEC
DEF
idle
00
PARAMETER_BIN
DEF
starting
01
PARAMETER_BIN
DEF
receving
10
PARAMETER_BIN
DEF
}
# end
# entity
uart_top
# storage
db|uart_top.(0).cnf
db|uart_top.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_top.v
86cd694b846a0fedf2217da47f62cf5
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
uart_receive
# storage
db|uart_top.(6).cnf
db|uart_top.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_receive.v
2453a469a73c5598ac6d12ee1c44a8d
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
state0
0
PARAMETER_BIN
DEF
state1
1
PARAMETER_BIN
DEF
}
# hierarchies {
uart_receive:uart_receiver_a
}
# end
# complete