uart_top.tan.qmsg

Uart port 是一段不错的

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sel_baud_rate\[1\] register uart_emitter:uart_emitter_a\|serial register uart_receive:uart_receiver_a\|bus\[5\] 123.37 MHz 8.106 ns Internal " "Info: Clock \"sel_baud_rate\[1\]\" has Internal fmax of 123.37 MHz between source register \"uart_emitter:uart_emitter_a\|serial\" and destination register \"uart_receive:uart_receiver_a\|bus\[5\]\" (period= 8.106 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.364 ns + Longest register register " "Info: + Longest register to register delay is 2.364 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns uart_emitter:uart_emitter_a\|serial 1 REG LC10_7_E2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC10_7_E2; Fanout = 11; REG Node = 'uart_emitter:uart_emitter_a\|serial'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { uart_emitter:uart_emitter_a|serial } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.090 ns) + CELL(0.358 ns) 1.609 ns uart_receive:uart_receiver_a\|bus\[0\]~15 2 COMB LC9_5_E2 8 " "Info: 2: + IC(1.090 ns) + CELL(0.358 ns) = 1.609 ns; Loc. = LC9_5_E2; Fanout = 8; COMB Node = 'uart_receive:uart_receiver_a\|bus\[0\]~15'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.448 ns" { uart_emitter:uart_emitter_a|serial uart_receive:uart_receiver_a|bus[0]~15 } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.509 ns) 2.364 ns uart_receive:uart_receiver_a\|bus\[5\] 3 REG LC10_5_E2 1 " "Info: 3: + IC(0.246 ns) + CELL(0.509 ns) = 2.364 ns; Loc. = LC10_5_E2; Fanout = 1; REG Node = 'uart_receive:uart_receiver_a\|bus\[5\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.755 ns" { uart_receive:uart_receiver_a|bus[0]~15 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.028 ns ( 43.49 % ) " "Info: Total cell delay = 1.028 ns ( 43.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.336 ns ( 56.51 % ) " "Info: Total interconnect delay = 1.336 ns ( 56.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "2.364 ns" { uart_emitter:uart_emitter_a|serial uart_receive:uart_receiver_a|bus[0]~15 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "2.364 ns" { uart_emitter:uart_emitter_a|serial uart_receive:uart_receiver_a|bus[0]~15 uart_receive:uart_receiver_a|bus[5] } { 0.000ns 1.090ns 0.246ns } { 0.161ns 0.358ns 0.509ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.209 ns - Smallest " "Info: - Smallest clock skew is -5.209 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sel_baud_rate\[1\] destination 10.822 ns + Shortest register " "Info: + Shortest clock path from clock \"sel_baud_rate\[1\]\" to destination register is 10.822 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns sel_baud_rate\[1\] 1 CLK PIN_25 3 " "Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = PIN_25; Fanout = 3; CLK Node = 'sel_baud_rate\[1\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { sel_baud_rate[1] } "NODE_NAME" } "" } } { "uart_top.v" "" { Text "E:/verilog/uart/uart_top.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.378 ns) + CELL(0.879 ns) 6.497 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~33 2 COMB LC10_2_D1 1 " "Info: 2: + IC(4.378 ns) + CELL(0.879 ns) = 6.497 ns; Loc. = LC10_2_D1; Fanout = 1; COMB Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~33'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "5.257 ns" { sel_baud_rate[1] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.260 ns) + CELL(0.879 ns) 7.636 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~34 3 COMB LC10_1_D1 30 " "Info: 3: + IC(0.260 ns) + CELL(0.879 ns) = 7.636 ns; Loc. = LC10_1_D1; Fanout = 30; COMB Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~34'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.139 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.186 ns) + CELL(0.000 ns) 10.822 ns uart_receive:uart_receiver_a\|bus\[5\] 4 REG LC10_5_E2 1 " "Info: 4: + IC(3.186 ns) + CELL(0.000 ns) = 10.822 ns; Loc. = LC10_5_E2; Fanout = 1; REG Node = 'uart_receive:uart_receiver_a\|bus\[5\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "3.186 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.998 ns ( 27.70 % ) " "Info: Total cell delay = 2.998 ns ( 27.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.824 ns ( 72.30 % ) " "Info: Total interconnect delay = 7.824 ns ( 72.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "10.822 ns" { sel_baud_rate[1] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "10.822 ns" { sel_baud_rate[1] sel_baud_rate[1]~out0 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } { 0.000ns 0.000ns 4.378ns 0.260ns 3.186ns } { 0.000ns 1.240ns 0.879ns 0.879ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sel_baud_rate\[1\] source 16.031 ns - Longest register " "Info: - Longest clock path from clock \"sel_baud_rate\[1\]\" to source register is 16.031 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns sel_baud_rate\[1\] 1 CLK PIN_25 3 " "Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = PIN_25; Fanout = 3; CLK Node = 'sel_baud_rate\[1\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { sel_baud_rate[1] } "NODE_NAME" } "" } } { "uart_top.v" "" { Text "E:/verilog/uart/uart_top.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.379 ns) + CELL(0.879 ns) 6.498 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~32 2 COMB LC7_2_D1 1 " "Info: 2: + IC(4.379 ns) + CELL(0.879 ns) = 6.498 ns; Loc. = LC7_2_D1; Fanout = 1; COMB Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~32'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "5.258 ns" { sel_baud_rate[1] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.358 ns) 7.102 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~33 3 COMB LC10_2_D1 1 " "Info: 3: + IC(0.246 ns) + CELL(0.358 ns) = 7.102 ns; Loc. = LC10_2_D1; Fanout = 1; COMB Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~33'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.604 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.260 ns) + CELL(0.879 ns) 8.241 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~34 4 COMB LC10_1_D1 30 " "Info: 4: + IC(0.260 ns) + CELL(0.879 ns) = 8.241 ns; Loc. = LC10_1_D1; Fanout = 30; COMB Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~34'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.139 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.216 ns) + CELL(0.496 ns) 11.953 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp0\[2\] 5 REG LC5_2_E1 24 " "Info: 5: + IC(3.216 ns) + CELL(0.496 ns) = 11.953 ns; Loc. = LC5_2_E1; Fanout = 24; REG Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "3.712 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.078 ns) + CELL(0.000 ns) 16.031 ns uart_emitter:uart_emitter_a\|serial 6 REG LC10_7_E2 11 " "Info: 6: + IC(4.078 ns) + CELL(0.000 ns) = 16.031 ns; Loc. = LC10_7_E2; Fanout = 11; REG Node = 'uart_emitter:uart_emitter_a\|serial'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.078 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] uart_emitter:uart_emitter_a|serial } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.852 ns ( 24.03 % ) " "Info: Total cell delay = 3.852 ns ( 24.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.179 ns ( 75.97 % ) " "Info: Total interconnect delay = 12.179 ns ( 75.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "16.031 ns" { sel_baud_rate[1] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] uart_emitter:uart_emitter_a|serial } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "16.031 ns" { sel_baud_rate[1] sel_baud_rate[1]~out0 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] uart_emitter:uart_emitter_a|serial } { 0.000ns 0.000ns 4.379ns 0.246ns 0.260ns 3.216ns 4.078ns } { 0.000ns 1.240ns 0.879ns 0.358ns 0.879ns 0.496ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "10.822 ns" { sel_baud_rate[1] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "10.822 ns" { sel_baud_rate[1] sel_baud_rate[1]~out0 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } { 0.000ns 0.000ns 4.378ns 0.260ns 3.186ns } { 0.000ns 1.240ns 0.879ns 0.879ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "16.031 ns" { sel_baud_rate[1] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] uart_emitter:uart_emitter_a|serial } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "16.031 ns" { sel_baud_rate[1] sel_baud_rate[1]~out0 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] uart_emitter:uart_emitter_a|serial } { 0.000ns 0.000ns 4.379ns 0.246ns 0.260ns 3.216ns 4.078ns } { 0.000ns 1.240ns 0.879ns 0.358ns 0.879ns 0.496ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 5 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" {  } { { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "2.364 ns" { uart_emitter:uart_emitter_a|serial uart_receive:uart_receiver_a|bus[0]~15 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "2.364 ns" { uart_emitter:uart_emitter_a|serial uart_receive:uart_receiver_a|bus[0]~15 uart_receive:uart_receiver_a|bus[5] } { 0.000ns 1.090ns 0.246ns } { 0.161ns 0.358ns 0.509ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "10.822 ns" { sel_baud_rate[1] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "10.822 ns" { sel_baud_rate[1] sel_baud_rate[1]~out0 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } { 0.000ns 0.000ns 4.378ns 0.260ns 3.186ns } { 0.000ns 1.240ns 0.879ns 0.879ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "16.031 ns" { sel_baud_rate[1] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] uart_emitter:uart_emitter_a|serial } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "16.031 ns" { sel_baud_rate[1] sel_baud_rate[1]~out0 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] uart_emitter:uart_emitter_a|serial } { 0.000ns 0.000ns 4.379ns 0.246ns 0.260ns 3.216ns 4.078ns } { 0.000ns 1.240ns 0.879ns 0.358ns 0.879ns 0.496ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sel_baud_rate\[0\] register uart_emitter:uart_emitter_a\|serial register uart_receive:uart_receiver_a\|bus\[5\] 122.97 MHz 8.132 ns Internal " "Info: Clock \"sel_baud_rate\[0\]\" has Internal fmax of 122.97 MHz between source register \"uart_emitter:uart_emitter_a\|serial\" and destination register \"uart_receive:uart_receiver_a\|bus\[5\]\" (period= 8.132 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.364 ns + Longest register register " "Info: + Longest register to register delay is 2.364 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns uart_emitter:uart_emitter_a\|serial 1 REG LC10_7_E2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC10_7_E2; Fanout = 11; REG Node = 'uart_emitter:uart_emitter_a\|serial'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { uart_emitter:uart_emitter_a|serial } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.090 ns) + CELL(0.358 ns) 1.609 ns uart_receive:uart_receiver_a\|bus\[0\]~15 2 COMB LC9_5_E2 8 " "Info: 2: + IC(1.090 ns) + CELL(0.358 ns) = 1.609 ns; Loc. = LC9_5_E2; Fanout = 8; COMB Node = 'uart_receive:uart_receiver_a\|bus\[0\]~15'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.448 ns" { uart_emitter:uart_emitter_a|serial uart_receive:uart_receiver_a|bus[0]~15 } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.509 ns) 2.364 ns uart_receive:uart_receiver_a\|bus\[5\] 3 REG LC10_5_E2 1 " "Info: 3: + IC(0.246 ns) + CELL(0.509 ns) = 2.364 ns; Loc. = LC10_5_E2; Fanout = 1; REG Node = 'uart_receive:uart_receiver_a\|bus\[5\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.755 ns" { uart_receive:uart_receiver_a|bus[0]~15 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.028 ns ( 43.49 % ) " "Info: Total cell delay = 1.028 ns ( 43.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.336 ns ( 56.51 % ) " "Info: Total interconnect delay = 1.336 ns ( 56.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "2.364 ns" { uart_emitter:uart_emitter_a|serial uart_receive:uart_receiver_a|bus[0]~15 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "2.364 ns" { uart_emitter:uart_emitter_a|serial uart_receive:uart_receiver_a|bus[0]~15 uart_receive:uart_receiver_a|bus[5] } { 0.000ns 1.090ns 0.246ns } { 0.161ns 0.358ns 0.509ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.235 ns - Smallest " "Info: - Smallest clock skew is -5.235 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sel_baud_rate\[0\] destination 10.314 ns + Shortest register " "Info: + Shortest clock path from clock \"sel_baud_rate\[0\]\" to destination register is 10.314 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns sel_baud_rate\[0\] 1 CLK PIN_24 3 " "Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = PIN_24; Fanout = 3; CLK Node = 'sel_baud_rate\[0\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { sel_baud_rate[0] } "NODE_NAME" } "" } } { "uart_top.v" "" { Text "E:/verilog/uart/uart_top.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.363 ns) + CELL(0.879 ns) 6.482 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~31 2 COMB LC1_2_D1 1 " "Info: 2: + IC(4.363 ns) + CELL(0.879 ns) = 6.482 ns; Loc. = LC1_2_D1; Fanout = 1; COMB Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~31'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "5.242 ns" { sel_baud_rate[0] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.288 ns) + CELL(0.358 ns) 7.128 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~34 3 COMB LC10_1_D1 30 " "Info: 3: + IC(0.288 ns) + CELL(0.358 ns) = 7.128 ns; Loc. = LC10_1_D1; Fanout = 30; COMB Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~34'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.646 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.186 ns) + CELL(0.000 ns) 10.314 ns uart_receive:uart_receiver_a\|bus\[5\] 4 REG LC10_5_E2 1 " "Info: 4: + IC(3.186 ns) + CELL(0.000 ns) = 10.314 ns; Loc. = LC10_5_E2; Fanout = 1; REG Node = 'uart_receive:uart_receiver_a\|bus\[5\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "3.186 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.477 ns ( 24.02 % ) " "Info: Total cell delay = 2.477 ns ( 24.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.837 ns ( 75.98 % ) " "Info: Total interconnect delay = 7.837 ns ( 75.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "10.314 ns" { sel_baud_rate[0] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "10.314 ns" { sel_baud_rate[0] sel_baud_rate[0]~out0 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } { 0.000ns 0.000ns 4.363ns 0.288ns 3.186ns } { 0.000ns 1.240ns 0.879ns 0.358ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}